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11. 发明授权

US4969087A Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：US4969087A
公开(公告)日：1990-11-06
申请号：US116862
申请日：1987-11-04
申请人： Kouji Tanagawa , Tomoaki Yoshida
发明人： Kouji Tanagawa , Tomoaki Yoshida
IPC分类号： G06F11/22 , G06F11/34 , G06F11/36 , G06F15/78
CPC分类号： G06F11/3648 , G06F11/3466 , G06F15/786 , G06F11/348
摘要： In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through the internal bus and produces control signals for controlling the operations of the circuit elements, the data written in each of the circuit elements is transmitted to the internal bus during execution of any one of instructions involving transfer of data into the circuit element, and output terminals are provided for outputting part of the control signals from the control circuit and part of the output signals from the circuit elements through the internal bus, the control signals including write control signals for writing data in the circuit elements.
摘要翻译：在包括连接到内部总线并能够存储数据或算术运算的电路元件的评估单片微计算机中，需要在微计算机外部知道电路元件的内容，控制电路解码通过内部总线，并且产生用于控制电路元件的操作的控制信号，在执行包括将数据传送到电路元件中的任何一个指令的执行期间，写入每个电路元件的数据被发送到内部总线，并且输出端子用于从控制电路输出部分控制信号和通过内部总线从电路元件输出的部分输出信号，该控制信号包括用于在电路元件中写入数据的写入控制信号。

12. 发明授权

US4788454A Power-on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US4788454A
公开(公告)日：1988-11-29
申请号：US74251
申请日：1987-07-16
申请人： Kouji Tanagawa , Tomoaki Yoshida
发明人： Kouji Tanagawa , Tomoaki Yoshida
IPC分类号： G01R19/165 , H03K17/22 , H03K3/01 , H03K5/153 , H03K17/16 , H03K19/017
CPC分类号： H03K17/223 , G01R19/16519 , H03K17/22
摘要： A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.
摘要翻译：用于逻辑电路的复位电路包括MOS晶体管，其具有耦合到电源的栅极，接收复位输入的源极和当复位输入为高电平且电源电压降至预定阈值以下时其电位为高的漏极，当MOS晶体管的漏极为高电平且在复位输入为低电平时复位的触发器，以及当触发器处于置位状态时产生复位输出的电路，复位输出被施加到逻辑电路。

13. 发明授权

US5231637A Apparatus for testing a PLA by measuring a current consumed by the PLO when activated with known codes 失效
标题翻译：用于通过测量当用已知代码激活时由PLO消耗的电流来测试PLA的装置
公开(公告)号：US5231637A
公开(公告)日：1993-07-27
申请号：US809127
申请日：1991-12-18
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G01R31/3185 , G06F9/30 , G06F9/318 , G06F11/273 , H03K19/096
CPC分类号： G06F9/30181 , G01R31/318516 , G06F9/30145 , H03K19/096 , G06F11/2736
摘要： A test circuit for testing a programmable array of a microprocessor including an instruction register for receiving an instruction signal from a data bus in response to a control signal and for outputting the received instruction signal to output lines, and a programmable logic array having a plurality of NAND circuits each forming a conductive path between first and second terminals when a predetermined instruction signal is received thereby from the register. Each of the NAND circuits includes a first terminal, a second terminal and a plurality of MOSFETs each having a first, a second and a gate electrode with the gate electrode coupled to an output line of the instruction register, and with the first and second electrodes being connected in series between the respective first and second terminals. A first precharge circuit is coupled to the first terminal of the NAND circuits, to a test terminal for providing a test signal and to a precharge terminal for providing a precharge signal, with this first precharge circuit supplying a first potential level to the first terminal of the NAND circuits in response to either the precharge signal or the test signal. A second precharge circuit is coupled to the second terminal of the NAND circuits, to the precharge terminal and to a power supply terminal for supplying a second potential level, with the second precharge circuit supplying the second potential level to the second terminal of the NAND circuits in response to the precharge signal. The current flowing through the power supply terminal, and thus through a conductive NAND circuit or circuits when the first and second potential levels are present, can then be measured to test the array.
摘要翻译：一种用于测试微处理器的可编程阵列的测试电路，包括用于响应于控制信号从数据总线接收指令信号并将接收到的指令信号输出到输出线的指令寄存器，以及具有多个当从寄存器接收到预定的指令信号时，各自形成第一和第二端子之间的导电路径的NAND电路。每个NAND电路包括第一端子，第二端子和多个MOSFET，每个MOSFET具有第一，第二和第二栅极，栅极连接到指令寄存器的输出线，并且与第一和第二电极在相应的第一和第二端子之间串联连接。第一预充电电路耦合到NAND电路的第一端子，提供给测试信号的测试端子和用于提供预充电信号的预充电端子，该第一预充电电路将第一电位电平提供给第一电位电平 NAND电路响应于预充电信号或测试信号。第二预充电电路与NAND电路的第二端子耦合到预充电端子和用于提供第二电位电平的电源端子，第二预充电电路将第二电位电平提供给NAND电路的第二端子响应于预充电信号。然后可以测量流过电源端子的电流，并且因此通过导电的NAND电路或电路在第一和第二电位电平存在时，测试该阵列。

14. 发明授权

US5117380A Random number generator driven by independent clock pulses asynchronously with system clock pulses 失效
标题翻译：独立时钟脉冲驱动的随机数发生器与系统时钟脉冲不相关
公开(公告)号：US5117380A
公开(公告)日：1992-05-26
申请号：US701375
申请日：1991-05-13
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F7/586
摘要： A random number generator built into an integrated circuit has at least one oscillator that generates clock pulses independent of the integrated circuit's system clock, at least two counters for counting those clock pulses, and read-out means for outputting the contents of the counters in response to a read signal. The random number generator accordingly has an extremely simple circuit configuration, but is capable of generating random numbers at a rapid rate.

15. 发明授权

US5059828A Programmable logic array circuit having a gate to control an output condition state of a latch thereof 失效
标题翻译：具有门控的控制其输出状态的可编程逻辑阵列电路
公开(公告)号：US5059828A
公开(公告)日：1991-10-22
申请号：US498269
申请日：1990-03-23
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A programmable logic array circuit which has a decoder, a sense amplifier and a latching circuit. The decoder decodes an instruction code into an output signal after a first precharge timing. The latching circuit latches the output signal from the decoder immediately before a second precharge timing. The gate circuit controls an output operation of the latching circuit in response to a prescribed timing signal.

16. 发明授权

US4566111A Watchdog timer 失效
标题翻译：看门狗定时器
公开(公告)号：US4566111A
公开(公告)日：1986-01-21
申请号：US547932
申请日：1983-11-02
申请人： Kouji Tanagawa
发明人： Kouji Tanagawa
IPC分类号： G06F11/30 , G01R29/027 , G06F11/00
CPC分类号： G06F11/0757 , G01R29/0273
摘要： A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (W.sub.T) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (W.sub.T), a counter (4) which is incremented by a clock pulse (.phi.), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F.sub.1) for storing said coincidence output signal for one period of said clock pulse (.phi.), a second flip-flop (F.sub.2) for storing said coincidence output signal upon receipt of said clock pulse (.phi.), a third flip-flop (F.sub.3) for storing output of said second flip-flop (F.sub.2) upon receipt of said clock pulse (.phi.), an AND circuit (G.sub.1) for providing logical product of reverse output (Q.sub.1) of said first flip-flop (F.sub.1) and said writing signal (W.sub.T), and an OR circuit (G.sub. 2) for receiving an output of said third flip-flop (F.sub.3) and an output of said AND circuit (G.sub.1) and producing an alarm signal NG which indicates an error of a computer to be monitored.
摘要翻译：用于监视计算机的操作的看门狗定时器监视由每个执行程序的指令产生的写入信号（WT）的周期是否处于预定持续时间内。当前的看门狗定时器包括一个用于在接收到写入信号（WT）时存储预定的DATA的寄存器（2），一个由时钟脉冲（phi）递增的计数器（4），用于提供符合输出信号当所述计数器的内容在所述寄存器（2）中达到所述预定的DATA时，用于存储所述时钟脉冲（phi）的一个周期的所述一致输出信号的第一触发器（F1），用于在接收到所述时钟脉冲（phi）时存储所述符合输出信号;第三触发器（F3），用于在接收到所述时钟脉冲（phi）时存储所述第二触发器（F2）的输出; AND电路），用于提供所述第一触发器（F1）和所述写入信号（WT）的反向输出（＆amp; upbar＆Q1）和用于接收所述第三触发器（F3）的输出的OR电路（G 2）和所述AND电路（G1）的输出，并产生指示要监视的计算机的错误的报警信号NG 。

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