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    • 12. 发明申请
    • Method and apparatus for digital phase generation at high frequencies
    • 高频数字相位生成方法及装置
    • US20060192601A1
    • 2006-08-31
    • US11413790
    • 2006-04-28
    • Kang Kim
    • Kang Kim
    • H03L7/06
    • H03L7/0814G11C7/22G11C7/222G11C11/4076H03L7/0805H03L7/0812H03L7/0818H03L7/10
    • An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjust delays of the first aligned phase signal and the N phase aligned signals.
    • 一种用于产生相位相关时钟的装置和方法,包括将时钟输入延迟周期延迟幅度以产生周期延迟信号,并且公开N个延迟抽头。 每个延迟抽头具有等于周期延迟幅度的分数量的延迟。 该方法还包括通过对准幅度延迟时钟输入以产生第一对准的相位信号,并且通过对准幅度的分数量来延迟N个延迟抽头中的每一个,以产生N个相位对准的信号。 反馈回路由第一对准相位信号和周期延迟信号之间的相位比较闭合。 相位比较结果用于调整周期延迟幅度,调整周期延迟信号和N个延迟抽头的延迟,并调整对准幅度,调整第一对准相位信号和N相对齐信号的延迟。
    • 15. 发明申请
    • Digital automatic white balance device
    • 数码自动白平衡装置
    • US20050122408A1
    • 2005-06-09
    • US10759187
    • 2004-01-20
    • Hyung ParkWon ChoiYeon LeeKang KimBoo KwakSang Park
    • Hyung ParkWon ChoiYeon LeeKang KimBoo KwakSang Park
    • H04N9/04H04N7/14H04N9/00H04N9/67H04N9/73
    • H04N9/735
    • A digital white balance device is simply implemented in a digital processing scheme by employing a grey world algorithm. In the device, a timing controller receives vertical and horizontal synchronization signals of an input image and produces a timing control signal. An RGB multiplier multiplies input RGB image data by RGB gains received from an RGB gain controller. A first YCbCr averaging unit converts input RGB image data to YCbCr image data, and obtains first YCbCr averages of this YCbCr image data. A second YCbCr averaging unit converts output RGB image data to YCbCr image data, and obtains second YCbCr averages of this YCbCr image data. According to the timing control signal, the RGB gain controller compares the second YCbCr averages with predetermined target YCbCr averages, respectively, and obtains RGB gains based on the first YCbCr averages, according to the compared result, and provides them to the RGB multiplier.
    • 数字白平衡装置通过采用灰色世界算法简单地在数字处理方案中实现。 在该装置中,定时控制器接收输入图像的垂直和水平同步信号,并产生定时控制信号。 RGB乘法器通过从RGB增益控制器接收的RGB增益来乘法输入RGB图像数据。 第一YCbCr平均单元将输入RGB图像数据转换为YCbCr图像数据,并获得该YCbCr图像数据的第一YCbCr平均值。 第二YCbCr平均单元将输出RGB图像数据转换为YCbCr图像数据,并获得该YCbCr图像数据的第二YCbCr平均值。 根据定时控制信号,RGB增益控制器分别将第二YCbCr平均值与预定目标YCbCr平均值进行比较,并根据比较结果获得基于第一YCbCr平均值的RGB增益,并将其提供给RGB乘法器。
    • 19. 发明授权
    • Semiconductor device with buried gate and method for fabricating the same
    • 具有埋栅的半导体器件及其制造方法
    • US08120099B2
    • 2012-02-21
    • US12616609
    • 2009-11-11
    • Dae-Young SeoDoo-Kang Kim
    • Dae-Young SeoDoo-Kang Kim
    • H01L29/78
    • H01L29/4236H01L21/823437H01L27/10876
    • A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap.
    • 提供了半导体器件及其制造方法。 半导体器件包括形成在衬底中的沟槽,在沟槽的两侧形成在衬底中的接合区域,形成在沟槽表面上的第一栅极绝缘层,形成在第一栅极绝缘层上的第一掩埋导电层 以填充所述沟槽的一部分,形成在所述第一掩埋导电层和所述第一栅极绝缘层之间以在所述第一掩埋导电层和所述第一栅极绝缘层之间提供间隙的第二掩埋导电层,以及掩埋所述第二掩埋导电层的第二栅极绝缘层 在差距。