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11. 发明申请

US20090152724A1 IC INTERCONNECT FOR HIGH CURRENT 有权
标题翻译： IC互连高电流
公开(公告)号：US20090152724A1
公开(公告)日：2009-06-18
申请号：US11954866
申请日：2007-12-12
申请人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
发明人： Ping-Chuan Wang , Kimball M. Watson , Kai Xiu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line.
摘要翻译：公开了用于大电流器件的IC互连，其设计结构和方法。 IC互连的一个实施例包括位于电介质中的第一通孔，并在一端连接到高电流装置; 位于电介质中并在其另一端耦合到第一通孔的缓冲金属段; 以及多个第二通孔，其位于电介质中并且在一端处连接到缓冲金属段，并且在另一端处连接到金属电源线，其中所述缓冲金属段的长度短于金属电源线。

12. 发明申请

US20070001262A1 SOI bipolar transistors with reduced self heating 失效
标题翻译：具有自加热降低的SOI双极晶体管
公开(公告)号：US20070001262A1
公开(公告)日：2007-01-04
申请号：US11173540
申请日：2005-07-01
申请人： Qiqing Ouyang , Kai Xiu
发明人： Qiqing Ouyang , Kai Xiu
IPC分类号： H01L27/082
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203
摘要： A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.
摘要翻译：双极晶体管包括位于衬底上方的集电极; 以及将基板连接到集电体的导热路径。导热路径填充有诸如金属或多晶硅的导热材料。在一个实施例中，导热路径穿过收集器以从集电器提取热量并将其排出到基板。在替代实施例中，晶体管可以是垂直或横向装置。根据另一实施例，使用BiCMOS技术的集成电路包括具有从集电极到衬底以及可能的p沟道和n沟道MOSFET的热传导的pnp和npn双极晶体管。根据另一个实施例，一种用于在集成网络中制造晶体管的方法包括以下步骤：蚀刻通过集电器和衬底的导热路径，并填充导热材料，以为包括集电器的晶体管提供散热。

13. 发明授权

US07525162B2 Orientation-optimized PFETS in CMOS devices employing dual stress liners 失效
标题翻译：采用双重应力衬垫的CMOS器件中的取向优化PFETS
公开(公告)号：US07525162B2
公开(公告)日：2009-04-28
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 1 0] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译：在具有（110）表面取向且位于衬底中的硅层上提供PFET。设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。当PFET通道的方向与平面内[1 10]晶体方向的方位角之间时，主压缩纵向应变和次级拉伸横向应力的净效益最大化（110）硅层为约25°至约55°。

14. 发明申请

US20090065867A1 ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS 失效
标题翻译：使用双应力衬片的CMOS器件中的方位优化PFET
公开(公告)号：US20090065867A1
公开(公告)日：2009-03-12
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 10] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译：在具有（110）表面取向且位于衬底中的硅层上提供PFET。设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。当PFET通道的方向和平面内[1 10]晶体方向的方位角在（（））时，主压缩纵向应变和次拉伸横向应力的最大优点是最大化， 110）硅层为约25°至约55°。

15. 发明授权

US07375371B2 Structure and method for thermally stressing or testing a semiconductor device 有权
标题翻译：用于热应力或测试半导体器件的结构和方法
公开(公告)号：US07375371B2
公开(公告)日：2008-05-20
申请号：US11307324
申请日：2006-02-01
申请人： Giuseppe La Rosa , Kevin W. Kolvenbach , John Greg Massey , Ping-Chuan Wang , Kai Xiu
发明人： Giuseppe La Rosa , Kevin W. Kolvenbach , John Greg Massey , Ping-Chuan Wang , Kai Xiu
IPC分类号： H01L23/58 , H01L29/10 , G01R31/02
CPC分类号： G01R31/2856
摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.
摘要翻译：提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

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