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11. 发明申请

US20120145617A1 MULTI-FUNCTIONAL OPTION VALVE, MULTIFUNCTIONAL FULLY AUTOMATIC LIQUID CHROMATOGRAPHY SYSTEM INCLUDING THE SAME, AND METHOD FOR ANALYZING SAMPLE USING THE SAME 有权
标题翻译：多功能选择阀，包括其的多功能全自动液相色谱系统和使用其分析样品的方法
公开(公告)号：US20120145617A1
公开(公告)日：2012-06-14
申请号：US13397409
申请日：2012-02-15
申请人： Sang-Won Lee , Seok-Won Hyung , Jung Hwa Lee , Kyong-Chul Kim , Dong-Gi Mun
发明人： Sang-Won Lee , Seok-Won Hyung , Jung Hwa Lee , Kyong-Chul Kim , Dong-Gi Mun
IPC分类号： B01D15/10 , G01N30/84 , B22D41/16
CPC分类号： G01N30/08 , B01D15/14 , B01D15/16 , G01N30/20 , G01N2030/085 , G01N2030/201 , G01N2030/202
摘要： Provided is a multifunction selection valve for use in a liquid chromatography system. The multifunction selection valve includes multiple ports to which both ends of a 1st dimension separation column may be connected at a part thereof, the multifunction selection valve including: a fluid passing mode in which a fluid introduced thereto is not passed through the 1st dimension separation column but is discharged; a column passing mode in which the fluid introduced thereto is passed through the 1st dimension separation column and then discharged; and a fluid blocking mode in which the fluid is prevented from being introduced. When using the multifunction selection valve, it modifies the flow paths of chromatographic solvents so that the resultant multifunctional liquid chromatography system allows one-dimensional separation, two-dimensional separation, on-line digestion and on-line phosphopeptide enrichment by a single binary pump.
摘要翻译：提供一种用于液相色谱系统的多功能选择阀。所述多功能选择阀包括多个端口，所述第一尺寸分离柱的两端可以在其一端连接到所述多个端口，所述多功能选择阀包括：流体通过模式，其中导入的流体不通过所述第一尺寸分离柱但已经出院了引入其中的流体通过第一维分离柱然后排出的柱通过模式; 以及防止流体被引入的流体阻塞模式。当使用多功能选择阀时，它会修改色谱溶剂的流路，从而使得多功能液相色谱系统能够通过单个二元泵进行一维分离，二维分离，在线消化和在线磷酸肽浓缩。

12. 发明授权

US07999299B2 Semiconductor memory device having capacitor for peripheral circuit 失效
标题翻译：具有用于外围电路的电容器的半导体存储器件
公开(公告)号：US07999299B2
公开(公告)日：2011-08-16
申请号：US12264490
申请日：2008-11-04
申请人： Jung-Hwa Lee , Si-Woo Lee
发明人： Jung-Hwa Lee , Si-Woo Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/0629 , H01L28/40
摘要： Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.
摘要翻译：提供了具有外围电路电容器的半导体存储器件。在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。

13. 发明授权

US07883970B2 Semiconductor device having decoupling capacitor and method of fabricating the same 有权
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US07883970B2
公开(公告)日：2011-02-08
申请号：US12343035
申请日：2008-12-23
申请人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
发明人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/0805 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L29/66181 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.
摘要翻译：提供具有去耦电容器的半导体器件及其制造方法。半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。至少一个通道沟槽设置在半导体衬底的单元区域中。至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。栅电极设置在半导体衬底的单元区域中并填充沟槽。第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。栅极电介质层介于通道沟槽和栅电极之间。在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

14. 发明授权

US07474549B2 Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer 有权
标题翻译：位线均衡器，包括其的半导体存储器件以及用于制造位线均衡器的方法
公开(公告)号：US07474549B2
公开(公告)日：2009-01-06
申请号：US11756725
申请日：2007-06-01
申请人： Soo-bong Chang , Jung-hwa Lee
发明人： Soo-bong Chang , Jung-hwa Lee
IPC分类号： G11C5/06
CPC分类号： H01L27/10897 , G11C7/12 , G11C11/4094 , H01L27/0207
摘要： A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.
摘要翻译：位线均衡器，包括位线均衡器的半导体存储器件和用于制造位线均衡器的方法，其中位线均衡器包括：第一和第二多晶硅栅极，形成在靠近彼此之间，第一和第二多晶硅栅极之间具有预定的距离; 以及沿着第一和第二多晶硅栅极沿第二方向形成的多个均衡晶体管，均衡晶体管均衡位线对，均衡晶体管交替地形成在第一和第二多晶硅栅极附近。位线均衡器可以改变均衡晶体管的宽度，而与存储单元间距无关，以便改善均衡时间。

15. 发明授权

US07359280B2 Layout structure for sub word line drivers and method thereof 有权
标题翻译：子字线驱动器的布局结构及其方法
公开(公告)号：US07359280B2
公开(公告)日：2008-04-15
申请号：US11336831
申请日：2006-01-23
申请人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
发明人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11898
摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.
摘要翻译：子字线驱动器的布局结构及其方法。示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向子字线驱动器从第一子阵列块到第二子阵列块。该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

16. 发明申请

US20080024202A1 HIGH VOLTAGE GENERATING CIRCUIT PRESERVING CHARGE PUMPING EFFICIENCY 失效
标题翻译：高电压发生电路保护充电泵送效率
公开(公告)号：US20080024202A1
公开(公告)日：2008-01-31
申请号：US11865863
申请日：2007-10-02
申请人： Jeong-hoon KOOK , Jung-hwa LEE , Jung-suk KIM , Dae-hwan KIM
发明人： Jeong-hoon KOOK , Jung-hwa LEE , Jung-suk KIM , Dae-hwan KIM
IPC分类号： G05F3/02
CPC分类号： G11C5/145 , G11C11/4074 , H02M3/07
摘要： A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.
摘要翻译：公开了一种高压发生电路。在高电压产生电路中，升压节点由多个泵电路预充电并升压，然后放电到输出端子。在升压节点处的电压明显小于电源电压的情况下，升压节点处的电压升高到电源电压。在升压节点处的电压明显大于电源电压的情况下，防止在升压节点和电源电压之间形成电流路径，以保持升压节点处的电压明显。

17. 发明授权

US07309883B2 Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same 有权
标题翻译：能够防止由闩锁引起的电流的半导体装置及其形成方法
公开(公告)号：US07309883B2
公开(公告)日：2007-12-18
申请号：US10815448
申请日：2004-04-01
申请人： Soon-Hong Ahn , Jung-Hwa Lee
发明人： Soon-Hong Ahn , Jung-Hwa Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/0921 , H01L21/823878 , H01L21/823892
摘要： A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, and includes an insulating region and a second-type diffusion region outside the insulating region. The third well is adjacent to the second well and includes a first-type diffusion region that receives a first voltage. The insulating region inside the second well along with the first-type well diffusion region of the first well constitute a bipolar junction transistor that cuts off current flowing from the first well to the third well.
摘要翻译：半导体器件包括第一，第二和第三阱。第一阱连接到外部引脚连接到的焊盘，并且包括接收阱偏置电压的第一类型扩散区域。第二阱与第一阱相邻，并且在绝缘区域之外包括绝缘区域和第二类型扩散区域。第三阱与第二阱相邻并且包括接收第一电压的第一类型扩散区域。第二阱内的绝缘区域与第一阱的第一型阱扩散区域一起构成双极结型晶体管，其切断从第一阱流向第三阱的电流。

18. 发明申请

US20070152280A1 Semiconductor memory device with triple well structure and method of manufacturing the same 审中-公开
标题翻译：具有三重阱结构的半导体存储器件及其制造方法
公开(公告)号：US20070152280A1
公开(公告)日：2007-07-05
申请号：US11649774
申请日：2007-01-05
申请人： Jung-Hwa Lee , Jae-Young Lee
发明人： Jung-Hwa Lee , Jae-Young Lee
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823493 , H01L27/0928 , H01L27/105 , H01L27/1052
摘要： A semiconductor memory device may include a semiconductor substrate that may have a first conductivity type. A first buried layer may be formed in the semiconductor substrate and may have a second conductivity type opposite to the first type conductivity. A first well may be formed on the first buried layer and may have the first type conductivity. A second well may be formed in the first well over a first surface portion of the first buried layer and may have the second conductivity type. A second buried layer may be formed in the first well and on a second surface portion of the first buried layer and may have the first conductivity type. A third well may be formed in the first well and on the second buried layer and may have the second conductivity type.
摘要翻译：半导体存储器件可以包括可以具有第一导电类型的半导体衬底。可以在半导体衬底中形成第一掩埋层，并且可以具有与第一类型导电性相反的第二导电类型。第一阱可以形成在第一掩埋层上并且可以具有第一类型的导电性。可以在第一阱中的第一掩埋层的第一表面部分上形成第二阱，并且可以具有第二导电类型。可以在第一阱中和第一掩埋层的第二表面部分上形成第二掩埋层，并且可以具有第一导电类型。可以在第一阱和第二掩埋层中形成第三阱，并且可以具有第二导电类型。

19. 发明申请

US20070052013A1 Semiconductor device having decoupling capacitor and method of fabricating the same 失效
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US20070052013A1
公开(公告)日：2007-03-08
申请号：US11449959
申请日：2006-06-09
申请人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
发明人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/0805 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L29/66181 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.
摘要翻译：提供具有去耦电容器的半导体器件及其制造方法。半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。至少一个通道沟槽设置在半导体衬底的单元区域中。至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。栅电极设置在半导体衬底的单元区域中并填充沟槽。第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。栅极电介质层介于通道沟槽和栅电极之间。在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

20. 发明申请

US20060268035A1 Ink-jet image forming apparatus and method for compensating for defective nozzle 审中-公开
标题翻译：喷墨图像形成装置和补偿缺陷喷嘴的方法
公开(公告)号：US20060268035A1
公开(公告)日：2006-11-30
申请号：US11362715
申请日：2006-02-28
申请人： Jung-hwa Lee , Masahiko Habuka
发明人： Jung-hwa Lee , Masahiko Habuka
IPC分类号： B41J29/38
CPC分类号： B41J29/393 , B41J2/2139
摘要： An ink-jet image forming apparatus and method for compensating for a defective nozzle are provided. The ink-jet image forming apparatus includes a recording medium transferring unit to transfer a recording medium in a first direction, a printhead to extend substantially parallel with a second direction, the second direction transversing the first direction, on which a nozzle unit is defined, the nozzle unit having nozzles through which ink droplets are ejected onto the recording medium, a carriage with the printhead mounted thereon, a carriage transferring unit to reciprocate the carriage in the second direction, and a controller to synchronize operations of the recording medium transferring unit, the printhead, and the carriage transferring unit, and to print the ink droplets ejected by the nozzles in a desired position of the recording medium so as to disperse an effect of a defective nozzle. The method includes: receiving a printing environment, detecting the defective nozzle in the nozzle unit by a detecting unit, and reciprocating the printhead in a longitudinal direction to disperse an effect of the defective nozzle.
摘要翻译：提供了一种用于补偿有缺陷的喷嘴的喷墨图像形成装置和方法。喷墨图像形成装置包括：记录介质传送单元，用于沿第一方向传送记录介质;打印头，其基本上平行于第二方向延伸;第二方向横切第一方向，定义喷嘴单元; 所述喷嘴单元具有喷嘴，墨滴通过所述喷嘴喷射到所述记录介质上;滑架，其上安装有所述打印头;托架转移单元，用于沿所述第二方向往复运动;以及控制器，用于使所述记录介质传送单元，打印头和托架转印单元，并且将由喷嘴喷射的墨滴打印在记录介质的期望位置，以便分散有缺陷喷嘴的作用。该方法包括：接收打印环境，通过检测单元检测喷嘴单元中的有缺陷的喷嘴，并使打印头沿纵向往复运动以分散有缺陷喷嘴的影响。

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