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11. 发明授权

US07319345B2 Wide-range multi-phase clock generator 有权
标题翻译：宽范围多相时钟发生器
公开(公告)号：US07319345B2
公开(公告)日：2008-01-15
申请号：US11001865
申请日：2004-12-01
申请人： Ramin Farjad-rad , John W. Poulton , John Eble , Thomas H. Greer, III , Robert Palmer
发明人： Ramin Farjad-rad , John W. Poulton , John Eble , Thomas H. Greer, III , Robert Palmer
IPC分类号： H03K17/00
CPC分类号： G06F1/06 , G06F1/04 , H03L7/0812 , H03L7/0995 , H03L7/0998
摘要： A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.
摘要翻译：一种具有第一时钟发生电路，分频器电路和多个多路复用器的宽范围多相时钟发生器。第一时钟产生电路产生多个第一时钟信号，每个第一时钟信号具有第一频率和多个不同相位角中的相应一个。分频器电路从第一时钟发生电路接收多个第一时钟信号，并产生多个第二时钟信号，每个具有第二频率和多个不同相位角中的相应一个。多路复用器各自具有耦合以接收第一时钟信号中的相应一个的第一输入和耦合以接收具有与第一时钟信号之一基本相同的相位角的第二时钟信号中的相应一个的第二输入。

12. 发明申请

US20060062341A1 Fast-lock clock-data recovery system 审中-公开
标题翻译：快速锁定时钟数据恢复系统
公开(公告)号：US20060062341A1
公开(公告)日：2006-03-23
申请号：US11016513
申请日：2004-12-17
申请人： John Edmondson , John Eble , Ramin Farjad-rad , Shadi Barakat
发明人： John Edmondson , John Eble , Ramin Farjad-rad , Shadi Barakat
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/091 , H03L7/107 , H04L7/0025 , H04L7/0337
摘要： A fast-locking clock-data recovery (CDR) system. The CDR system slews the phase of a sampling clock signal at a first slew rate in response to detecting an out-of-alignment condition between a first sampling clock signal and a data signal. Then, after exiting the out-of-alignment condition, the CDR system slews the phase of the sampling clock signal at a second, slower slew rate.
摘要翻译：快速锁定时钟数据恢复（CDR）系统。响应于检测到第一采样时钟信号和数据信号之间的不对齐状态，CDR系统以第一转换速率旋转采样时钟信号的相位。然后，在退出不对准状态之后，CDR系统以第二个较慢的转换速率旋转采样时钟信号的相位。

13. 发明申请

US20110127990A1 FREQUENCY RESPONSIVE BUS CODING 有权
标题翻译：频率响应总线编码
公开(公告)号：US20110127990A1
公开(公告)日：2011-06-02
申请号：US12999495
申请日：2009-06-18
申请人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
发明人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
IPC分类号： G01R23/165
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.
摘要翻译：数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

14. 发明申请

US20080094109A1 WIDE-RANGE MULTI-PHASE CLOCK GENERATOR 审中-公开
标题翻译：宽范围多相时钟发生器
公开(公告)号：US20080094109A1
公开(公告)日：2008-04-24
申请号：US11963747
申请日：2007-12-21
申请人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
发明人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
IPC分类号： H03K17/00
CPC分类号： G06F1/06 , G06F1/04 , H03L7/0812 , H03L7/0995 , H03L7/0998
摘要： A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.
摘要翻译：一种具有第一时钟发生电路，分频器电路和多个多路复用器的宽范围多相时钟发生器。第一时钟产生电路产生多个第一时钟信号，每个第一时钟信号具有第一频率和多个不同相位角中的相应一个。分频器电路从第一时钟发生电路接收多个第一时钟信号，并产生多个第二时钟信号，每个具有第二频率和多个不同相位角中的相应一个。多路复用器各自具有耦合以接收第一时钟信号中的相应一个的第一输入和耦合以接收具有与第一时钟信号之一基本相同的相位角的第二时钟信号中的相应一个的第二输入。

15. 发明申请

US20050258883A1 Wide-range multi-phase clock generator 有权
标题翻译：宽范围多相时钟发生器
公开(公告)号：US20050258883A1
公开(公告)日：2005-11-24
申请号：US11001865
申请日：2004-12-01
申请人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
发明人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
IPC分类号： G06F1/04 , G06F1/06 , G06F1/10 , H03L7/081 , H03L7/099 , H04L7/033 , H03L7/06
CPC分类号： G06F1/06 , G06F1/04 , H03L7/0812 , H03L7/0995 , H03L7/0998
摘要： A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.
摘要翻译：一种具有第一时钟发生电路，分频器电路和多个多路复用器的宽范围多相时钟发生器。第一时钟产生电路产生多个第一时钟信号，每个第一时钟信号具有第一频率和多个不同相位角中的相应一个。分频器电路从第一时钟发生电路接收多个第一时钟信号，并产生多个第二时钟信号，每个具有第二频率和多个不同相位角中的相应一个。多路复用器各自具有耦合以接收第一时钟信号中的相应一个的第一输入和耦合以接收具有与第一时钟信号之一基本相同的相位角的第二时钟信号中的相应一个的第二输入。

16. 发明授权

US2757476A Fishing fly 失效
标题翻译：钓鱼飞
公开(公告)号：US2757476A
公开(公告)日：1956-08-07
申请号：US24300251
申请日：1951-08-22
申请人： JOHN EBLE
发明人： PENDER JOSEPH D
IPC分类号： A01K85/08
CPC分类号： A01K85/08

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