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11. 发明授权

US5627987A Memory management and protection system for virtual memory in computer system 失效
标题翻译：计算机系统虚拟内存的内存管理和保护系统
公开(公告)号：US5627987A
公开(公告)日：1997-05-06
申请号：US21098
申请日：1993-02-23
申请人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
发明人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1458 , G06F12/109 , G06F12/1483 , G06F12/1491 , G06F2212/656
摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
摘要翻译：一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序，将搜索与当前节目号匹配的那个。此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

12. 发明授权

US5552250A Method of manufacturing reticle 失效
标题翻译：制作掩模版的方法
公开(公告)号：US5552250A
公开(公告)日：1996-09-03
申请号：US334065
申请日：1994-11-04
申请人： Hiroshi Nozue
发明人： Hiroshi Nozue
IPC分类号： G03F1/76 , G03F1/78 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/78 , G03F7/2063
摘要： A method of manufacturing a reticle having a desired pattern, includes the step of projecting electron beams to a mask blank including a glass substrate on which an electron beam sensitive layer is applied. The mask blank is held in place in the same situation as a situation in which the reticle is held when a stepper exposes a semiconductor wafer to light through said reticle. For instance, the mask blank being in place so that the electron beam sensitive layer faces downwardly and the electron beams is projected from a bottom of the layer. The method can eliminate dimensional errors of a pattern and a dislocation of a pattern on a semiconductor wafer which might occur due to a curvature of a reticle.
摘要翻译：制造具有期望图案的掩模版的方法包括将电子束投射到包括其上施加有电子束敏感层的玻璃基板的掩模坯料的步骤。当步进器将半导体晶片暴露于通过所述掩模版的光时，掩模毛坯在与保持掩模版的情况相同的情况下保持就位。例如，掩模坯料就位，使得电子束敏感层面向下并且电子束从该层的底部突出。该方法可以消除图案的尺寸误差和由于掩模版的曲率可能发生的半导体晶片上的图案的位错。

13. 发明授权

US09280466B2 Information processing device including memory management device managing access from processor to memory and memory management method 有权
标题翻译：信息处理装置，包括管理从处理器到存储器的访问的存储器管理装置和存储器管理方法
公开(公告)号：US09280466B2
公开(公告)日：2016-03-08
申请号：US12555952
申请日：2009-09-09
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/08 , G06F12/0888 , G06F2212/1036 , G06F2212/2022 , G06F2212/205 , G06F2212/7201
摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.
摘要翻译：根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数，在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

14. 发明授权

US5890189A Memory management and protection system for virtual memory in computer system 失效
标题翻译：计算机系统虚拟内存的内存管理和保护系统
公开(公告)号：US5890189A
公开(公告)日：1999-03-30
申请号：US753944
申请日：1996-12-03
申请人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
发明人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1458 , G06F12/109 , G06F12/1483 , G06F12/1491 , G06F2212/656
摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
摘要翻译：一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序，将搜索与当前节目号匹配的那个。此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

15. 发明授权

US5808310A Electron beam cell projection lithography method for correcting coulomb interaction effects 失效
标题翻译：用于校正库仑相互作用的电子束电池投影光刻方法
公开(公告)号：US5808310A
公开(公告)日：1998-09-15
申请号：US680643
申请日：1996-07-17
申请人： Hiroshi Yamashita , Takao Tamura , Hiroshi Nozue
发明人： Hiroshi Yamashita , Takao Tamura , Hiroshi Nozue
IPC分类号： G03F7/20 , H01J37/317 , H01L21/027 , H01J37/30
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/31769
摘要： Disclosed herein is a method of electron beam cell projection lithography, employing an electron beam which is shaped by a first aperture having a first opening and a second aperture having a plurality of second openings. The shaped electron beam is irradiated on a sample surface to expose plurality of patterns on the sample surface, wherein an exposure dose is determined according to an exposure intensity distribution function, thereby correcting a proximity effect, while the exposure dose is also controlled to correct for a beam blur induced by a Coulomb interaction effect. The exposure intensity distribution function includes a term for correcting the Coulomb interaction effect.
摘要翻译：本文公开了一种电子束电池投影光刻的方法，其采用电子束，该电子束由具有第一开口的第一孔和具有多个第二开口的第二孔形成。将成形的电子束照射在样品表面上以暴露样品表面上的多个图案，其中根据曝光强度分布函数确定曝光剂量，从而校正邻近效应，同时还控制曝光剂量以校正由库仑相互作用影响引起的光束模糊。曝光强度分布函数包括用于校正库仑相互作用效应的项。

16. 发明授权

US5745730A Apparatus and methods for implementing dedicated cache flushing 失效
标题翻译：用于实现专用缓存冲洗的装置和方法
公开(公告)号：US5745730A
公开(公告)日：1998-04-28
申请号：US653909
申请日：1996-05-28
申请人： Hiroshi Nozue , Yoshio Masubuchi
发明人： Hiroshi Nozue , Yoshio Masubuchi
IPC分类号： G06F11/14 , G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0831
摘要： A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external tag storage device stores state information to indicate the update of the data and a physical address corresponding to the updated data. An external tag reading device reads the state information stored in the external tag storage device, when the updated data on the cache memory is stored in a main memory. A bus command for flushing the updated data from the cache memory to the main memory is generated, based on the state of the tag read out from the external tag storage device. An invalid bus command generation device outputs an invalid bus command to the system bus through a FIFO.
摘要翻译：总线接口连接到系统总线，用于监视指示在处理器的高速缓冲存储器上更新数据的总线命令。如果在高速缓冲存储器上更新数据，则外部标签存储装置存储指示更新数据的状态信息和对应于更新数据的物理地址。当高速缓冲存储器上的更新数据存储在主存储器中时，外部标签读取装置读取存储在外部标签存储装置中的状态信息。基于从外部标签存储装置读出的标签的状态，生成用于将更新的数据从高速缓冲存储器刷新到主存储器的总线命令。无效总线命令生成装置通过FIFO向系统总线输出无效总线命令。

17. 发明授权

US5677756A Apparatus for exposing a semiconductor wafer to light including an illumination optical system comprising a glass substrate having light-permeable patterns 失效
标题翻译：用于将半导体晶片暴露于光的装置，包括具有透光图案的玻璃基板的照明光学系统
公开(公告)号：US5677756A
公开(公告)日：1997-10-14
申请号：US344652
申请日：1994-11-18
申请人： Hiroshi Nozue
发明人： Hiroshi Nozue
IPC分类号： G03F7/207 , G03F7/20 , H01L21/027 , H01L21/30
CPC分类号： G03F7/70091 , G03F7/70125
摘要： An apparatus for exposing a semiconductor wafer to light, includes a light source, a glass substrate, a mask having thereon a first pattern composed of light-impermeable material, a projection lens, and an illumination optical system for radiating light derived from the light source to said mask to thereby transfer the pattern on a semiconductor wafer. The glass substrate constitutes a part of the illumination optical system and has a plurality of second patterns which are light-permeable and each of which has a different dimension from each other. The second patterns preferably are square in shape, and also preferably a combination of squares and equilateral triangles in shape.
摘要翻译：一种用于将半导体晶片曝光的装置包括光源，玻璃基板，其上具有由不透光材料构成的第一图案的掩模，投影透镜和用于照射源自光源的光的照明光学系统到所述掩模，从而将图案转印到半导体晶片上。玻璃基板构成照明光学系统的一部分，并且具有多个第二图案，该第二图案是透光的，并且每个图案彼此具有不同的尺寸。第二图案优选地是正方形的，并且还优选地是正方形和等边三角形的组合。

18. 发明授权

US5607801A Direct patterning method of resist film using electron beam 失效
标题翻译：使用电子束的抗蚀剂膜的直接图案化方法
公开(公告)号：US5607801A
公开(公告)日：1997-03-04
申请号：US354807
申请日：1994-12-13
申请人： Hiroshi Nozue
发明人： Hiroshi Nozue
IPC分类号： H01L21/027 , G03F7/20 , H01J37/304 , G03F9/00 , G03C5/00
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , G03F7/2059 , H01J37/3045 , H01J2237/3175 , Y10S430/143
摘要： A direct patterning method using an electron beam, which-contains first and second steps. In the first step, a first beam of incident electrons accelerated at a first voltage is irradiated to an electron resist film and scanned. The first voltage is set so that the electrons penetrate the resist film to be back-scattered by a semiconductor substrate having an alignment mark and pass through the film again. Secondary electrons generated at the surface of the resist film due to the back-scattered electrons are detected by an electron detector to recognize the alignment mark. In the second step, a second beam of incident electrons accelerated at a second voltage lower than the first voltage is irradiated to the resist film and scanned by reference to the alignment mark to write a given pattern in the resist film. Since the back-scattered electrons from the first beam have sufficiently high energies, they can penetrate the resist film to reach its surface and generate many secondary electrons on the surface of the film. An electric signal produced from the secondary electrons is large in amplitude to increase the S/N, resulting in improvement in alignment accuracy.
摘要翻译：使用电子束的直接图案化方法，其包含第一和第二步骤。在第一步骤中，将以第一电压加速的入射电子的第一束照射到电子抗蚀剂膜并进行扫描。第一电压被设置为使得电子穿过抗蚀剂膜以被具有对准标记的半导体衬底反向散射并再次通过膜。通过电子检测器检测由于反向散射电子在抗蚀剂膜的表面产生的二次电子以识别对准标记。在第二步骤中，将以比第一电压低的第二电压加速的第二入射电子束照射到抗蚀剂膜上并通过参考对准标记进行扫描，以在抗蚀剂膜中写入给定的图案。由于来自第一光束的反向散射的电子具有足够高的能量，它们可以穿透抗蚀剂膜到达其表面并在膜的表面上产生许多二次电子。由二次电子产生的电信号的幅度大，以增加S / N，导致对准精度提高。

19. 发明申请

US20120191900A1 MEMORY MANAGEMENT DEVICE 审中-公开
标题翻译：内存管理设备
公开(公告)号：US20120191900A1
公开(公告)日：2012-07-26
申请号：US13351582
申请日：2012-01-17
申请人： Atsushi KUNIMATSU , Masaki MIYAGAWA , Hiroshi NOZUE , Kazuhiro KAWAGOME , Hiroto NAKAI , Hiroyuki SAKAMOTO , Tsutomu OWA , Tsutomu UNESAKI , Reina NISHINO , Kenichi MAEDA , Mari TAKADA
发明人： Atsushi KUNIMATSU , Masaki MIYAGAWA , Hiroshi NOZUE , Kazuhiro KAWAGOME , Hiroto NAKAI , Hiroyuki SAKAMOTO , Tsutomu OWA , Tsutomu UNESAKI , Reina NISHINO , Kenichi MAEDA , Mari TAKADA
IPC分类号： G06F12/02
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0638 , G06F3/0653 , G06F3/0679 , G06F12/0223 , G06F12/0246 , G06F12/06 , G06F2212/1016 , G06F2212/1036 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G06F2212/7208
摘要： A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
摘要翻译：本发明实施例的存储器管理装置响应于来自处理器的写入请求和读取请求，控制对包括非易失性半导体存储器和易失性半导体存储器的主存储器的写入和读取。存储器管理装置包括着色信息存储单元，该着色信息存储单元存储基于要写入到非易失性半导体存储器和易失性半导体存储器中的至少一个的写入目标数据的数据特性而生成的着色信息;以及写入管理单元，着色信息以确定从非易失性半导体存储器和易失性半导体存储器写入写目标数据的区域。

20. 发明授权

US08153996B2 Pattern forming apparatus and pattern forming method 有权
标题翻译：图案形成装置和图案形成方法
公开(公告)号：US08153996B2
公开(公告)日：2012-04-10
申请号：US12547958
申请日：2009-08-26
申请人： Takayuki Abe , Rikio Tomiyoshi , Hiroshi Nozue
发明人： Takayuki Abe , Rikio Tomiyoshi , Hiroshi Nozue
IPC分类号： G21K5/10 , H01L21/027 , H01J37/305
CPC分类号： H01J37/045 , B82Y10/00 , B82Y40/00 , H01J37/3026 , H01J37/3174 , H01J2237/0453
摘要： A pattern forming apparatus using lithography technique includes a stage configured to allow a target object to be placed thereon; a plurality of columns configured to form patterns on the target object by using a charged particle beam while moving relatively to the stage; a pattern forming rule setting unit configured to set a pattern forming rule depending on a position of broken one of the plurality of columns; a region setting unit configured to set regions so that unbroken ones of the plurality of columns respectively form a pattern in one of the regions; a plurality of control circuits each configured to control any one of the plurality of columns different from others of the plurality of columns controlled by others of the plurality of control circuits; and a pattern forming data processing unit configured to perform a converting process on pattern forming data for the regions set to output a corresponding data generated by the converting process to the control circuit of a corresponding one of the unbroken ones of the plurality of columns respectively.
摘要翻译：使用光刻技术的图案形成装置包括：被配置为允许将目标物体放置在其上的台; 多个列，被配置为通过在相对于所述载物台移动的同时使用带电粒子束在所述目标物体上形成图案; 图案形成规则设定单元，被配置为根据所述多个列中的断开的一个的位置来设置图案形成规则; 区域设定单元，被配置为设置区域，使得所述多个列中的不间断的列分别在所述区域之一中形成图案; 每个控制电路被配置为控制与多个控制电路中的其他控制电路控制的多个列中的其他列不同的多个列中的任一个; 以及图案形成数据处理单元，被配置为对所设置的区域的图案形成数据执行转换处理，以将分别对应的多个列中的不间断的相应数据的转换处理生成的相应数据输出到对应的一个。

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