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11. 发明申请

US20060001166A1 Circuit device and manufacturing method thereof 有权
标题翻译：电路装置及其制造方法
公开(公告)号：US20060001166A1
公开(公告)日：2006-01-05
申请号：US11165680
申请日：2005-06-24
申请人： Yusuke Igarashi , Takeshi Nakamura , Yasunori Inoue , Ryosuke Usui , Hideki Mizuhara
发明人： Yusuke Igarashi , Takeshi Nakamura , Yasunori Inoue , Ryosuke Usui , Hideki Mizuhara
IPC分类号： H01L23/48
CPC分类号： H01L23/5384 , H01L23/3128 , H01L24/48 , H01L2221/68377 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48465 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K3/4647 , H05K2201/0355 , H05K2201/09509 , H05K2201/09563 , H05K2203/0369 , H05K2203/0733 , H05K2203/1476 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.
摘要翻译：提供一种包括具有改善的散热性能的多层布线结构的电路装置及其制造方法。本发明的电路器件包括第一布线层和在插入第一绝缘层的同时层叠的第二布线层。第一布线层通过形成为穿透第一绝缘层的连接部分在期望位置连接到第二布线层。连接部分包括从第一布线层沿厚度方向突出的第一连接部分和从第二布线层沿厚度方向突出的第二连接部分。第一连接部和第二连接部在绝缘层的厚度方向的中间部彼此接触。

12. 发明申请

US20050067686A1 Semiconductor device containing stacked semiconductor chips and manufacturing method thereof 失效
标题翻译：含有堆叠半导体芯片的半导体装置及其制造方法
公开(公告)号：US20050067686A1
公开(公告)日：2005-03-31
申请号：US10951541
申请日：2004-09-28
申请人： Ryosuke Usui , Hideki Mizuhara , Takeshi Nakamura
发明人： Ryosuke Usui , Hideki Mizuhara , Takeshi Nakamura
IPC分类号： H01L23/12 , H01L21/68 , H01L23/31 , H01L23/498 , H01L25/16 , H05K3/24 , H05K3/30 , H05K3/34 , H05K3/38 , H01L23/02
CPC分类号： H01L21/6835 , H01L23/3128 , H01L23/498 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/16 , H01L2221/68345 , H01L2224/05554 , H01L2224/0603 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/13055 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K3/244 , H05K3/305 , H05K3/3452 , H05K3/381 , H05K2201/0989 , H05K2203/049 , H05K2203/095 , Y10S438/906 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.
摘要翻译：在电极膜上形成粘合膜，在其上形成涂膜。镍，铬，钼，钨，铝或它们的合金被用作粘合膜的构成材料。金，银，铂或它们的合金被用作涂膜的构成材料。

13. 发明申请

US20050067682A1 Semiconductor device containing stacked semiconductor chips and manufacturing method thereof 审中-公开
标题翻译：含有堆叠半导体芯片的半导体装置及其制造方法
公开(公告)号：US20050067682A1
公开(公告)日：2005-03-31
申请号：US10952203
申请日：2004-09-28
申请人： Ryosuke Usui , Hideki Mizuhara , Takeshi Nakamura
发明人： Ryosuke Usui , Hideki Mizuhara , Takeshi Nakamura
IPC分类号： H01L25/18 , H01L21/98 , H01L23/12 , H01L25/065 , H01L25/07 , H01L21/44 , H01L29/40
CPC分类号： H01L21/6835 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48465 , H01L2224/48475 , H01L2224/73204 , H01L2224/73265 , H01L2224/85051 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： Stacked interconnect layers each of which includes an interlayer dielectric film and an interconnect line made of copper, and solder resist layer formed as the top layer constitute a multilevel interconnect configuration. The first element, the second element and a circuit element are mounted on the surface of the configuration. The second element bonds to the first element by an adhesion layer. The upper surface of the first element is treated by plasma, and the second element is mounted on the surface.
摘要翻译：堆叠的互连层包括层间电介质膜和由铜构成的互连线，并且形成为顶层的阻焊层构成多层互连配置。第一元件，第二元件和电路元件安装在配置的表面上。第二元件通过粘合层与第一元件结合。第一元件的上表面通过等离子体处理，第二元件安装在表面上。

14. 发明授权

US06617240B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06617240B2
公开(公告)日：2003-09-09
申请号：US09748230
申请日：2000-12-27
申请人： Yasunori Inoue , Naoteru Matsubara , Hidetaka Nishimura , Hideki Mizuhara
发明人： Yasunori Inoue , Naoteru Matsubara , Hidetaka Nishimura , Hideki Mizuhara
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76825 , H01L21/76828
摘要： A method of fabricating a semiconductor device capable of attaining an excellent embedding characteristic also when an opening has a small diameter is obtained. According to this method of fabricating a semiconductor device, an interlayer dielectric film having an opening is formed. A first conductive member is formed in the opening by sputtering. In advance of formation of the first conductive member, first heat treatment is performed at a temperature capable of reducing the quantity of moisture and hydroxyl groups in the interlayer dielectric film. Thus, the interlayer dielectric film has a small quantity of moisture and hydroxyl groups when the first conductive member is embedded in the opening, whereby the embedding characteristic of the first conductive member is improved. Consequently, electric characteristics of a contact part can be improved also when the opening has a small diameter.
摘要翻译：获得了当开口具有小直径时也能够获得优异的嵌入特性的半导体器件的制造方法。根据制造半导体器件的这种方法，形成具有开口的层间绝缘膜。通过溅射在开口中形成第一导电构件。在形成第一导电部件之前，首先在能够降低层间电介质膜的湿度和羟基量的温度下进行热处理。因此，当第一导电部件嵌入开口时，层间电介质膜具有少量的水分和羟基，从而提高了第一导电部件的嵌入特性。因此，当开口具有小直径时，也可以提高接触部的电特性。

15. 发明授权

US06399478B2 Method of making a dual damascene structure with modified insulation 失效
标题翻译：制造具有改性绝缘材料的双镶嵌结构的方法
公开(公告)号：US06399478B2
公开(公告)日：2002-06-04
申请号：US09788661
申请日：2001-02-21
申请人： Naoteru Matsubara , Hideki Mizuhara
发明人： Naoteru Matsubara , Hideki Mizuhara
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/76807
摘要： A semiconductor device having a dual damascene structure having a highly reliable multilayered interconnection is applied to the present invention. A protective film (12) is formed on a first interconnection (11), and a modified SOG film (13a) is then provided thereon. An etch stopper film (14) is formed on the modified SOG film (13a), and a modified SOG film (15a) is then formed. The modified SOG film (15a), the etch stopper film (14), and the modified SOG film (13a) are etched away using a resist pattern, to form a via hole (17). The modified SOG film (15a) is etched away using the resist pattern, to form a recess (19) serving as a trench interconnection portion. The etch stopper film (14) and the protective film (12) which are exposed are removed, and the recess is filled with a conductive material (20), to form a conductive plug in the via hole and a second interconnection.
摘要翻译：具有高度可靠的多层互连的双镶嵌结构的半导体器件被应用于本发明。在第一互连（11）上形成保护膜（12），然后在其上提供改性SOG膜（13a）。在改性SOG膜（13a）上形成蚀刻停止膜（14），然后形成改性SOG膜（15a）。使用抗蚀剂图案蚀刻掉改性SOG膜（15a），蚀刻停止膜（14）和改性SOG膜（13a），以形成通孔（17）。使用抗蚀剂图案蚀刻掉改性SOG膜（15a），形成用作沟槽互连部分的凹部（19）。去除暴露的蚀刻停止膜（14）和保护膜（12），并且用导电材料（20）填充凹部，以在通孔和第二互连中形成导电塞。

16. 发明授权

US06235648B1 Semiconductor device including insulation film and fabrication method thereof 有权
标题翻译：包括绝缘膜的半导体器件及其制造方法
公开(公告)号：US06235648B1
公开(公告)日：2001-05-22
申请号：US09160044
申请日：1998-09-25
申请人： Hideki Mizuhara , Hiroyuki Watanabe , Naoteru Matsubara
发明人： Hideki Mizuhara , Hiroyuki Watanabe , Naoteru Matsubara
IPC分类号： H01L21461
CPC分类号： H01L21/76859 , H01L21/02126 , H01L21/02129 , H01L21/02137 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/02321 , H01L21/02351 , H01L21/31111 , H01L21/31116 , H01L21/31155 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76825 , H01L21/76829
摘要： A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.
摘要翻译：获得包括绝缘特性优异的绝缘膜的半导体器件。通过离子注入将硼离子引入到在有机SOG膜上形成的氮化硅膜的有机SOG膜中。通过这种硼注入，有机SOG膜的性质被改变。包括在膜中的水分和羟基与离子的剂量无关地大大降低。通过使用这样的改性SOG膜和氮化硅膜的分层膜作为层间绝缘膜或钝化膜，可以充分提高半导体器件的耐水性。

17. 发明授权

US06177343B1 Process for producing semiconductor devices including an insulating layer with an impurity 有权
标题翻译：用于制造包括具有杂质的绝缘层的半导体器件的工艺
公开(公告)号：US06177343B1
公开(公告)日：2001-01-23
申请号：US09429698
申请日：1999-10-28
申请人： Hiroyuki Watanabe , Hideki Mizuhara , Kaori Misawa , Masaki Hirase , Hiroyuki Aoe
发明人： Hiroyuki Watanabe , Hideki Mizuhara , Kaori Misawa , Masaki Hirase , Hiroyuki Aoe
IPC分类号： H01L214763
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/022 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02282 , H01L21/02321 , H01L21/02351 , H01L21/3115 , H01L21/31155 , H01L21/3121 , H01L21/316 , H01L21/31612 , H01L21/31625 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76877
摘要： A semiconductor device and a process for producing the same. The device has two conducting layers that are spaced from each other and an insulating film for electrically insulating these two conducting layers from each other. The insulating film contains contact holes with plugs being embedded therein so as to electrically connect these two conducting layers by the plugs. The process contains a step of forming the insulating film on the lower conducting layer. An impurity having a kinetic energy is introduced into the insulating film. Next, contact holes are formed in the insulating film, and then plugs are formed in the contact holes. An upper conducting layer is formed on the insulating film so as to be electrically connected to the plugs.
摘要翻译：半导体器件及其制造方法。该器件具有彼此间隔开的两个导电层和用于将这两个导电层彼此电绝缘的绝缘膜。绝缘膜包含嵌入其中的插塞的接触孔，以便通过插头将这两个导电层电连接。该方法包括在下导电层上形成绝缘膜的步骤。具有动能的杂质被引入到绝缘膜中。接下来，在绝缘膜中形成接触孔，然后在接触孔中形成插塞。在绝缘膜上形成上导电层以与插头电连接。

18. 发明授权

US5898221A Semiconductor device having upper and lower wiring layers 失效
标题翻译：具有上和下布线层的半导体器件
公开(公告)号：US5898221A
公开(公告)日：1999-04-27
申请号：US953822
申请日：1997-09-25
申请人： Hideki Mizuhara , Shinichi Tanimoto , Hiroyuki Watanabe , Yasunori Inoue
发明人： Hideki Mizuhara , Shinichi Tanimoto , Hiroyuki Watanabe , Yasunori Inoue
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53223 , H01L21/76838 , H01L23/5329 , H01L2924/0002
摘要： A semiconductor device having a semiconductor substrate and a wiring layer, which is doped with an impurity, located on the substrate. The semiconductor device has upper and lower wiring layers apart from each other. An electric insulating film electrically insulates between the upper and lower wiring layers. The insulating film has a contact hole. A wiring material is packed with the contact hole to electrically connect the upper and lower wiring layers. The impurity is contained in the lower wiring layer to decrease its resistivity.
摘要翻译：具有半导体衬底和掺杂有杂质的布线层的半导体器件位于衬底上。半导体器件具有彼此分开的上和下布线层。电绝缘膜在上下布线层之间电绝缘。绝缘膜具有接触孔。布线材料装有接触孔以电连接上下布线层。杂质包含在下布线层中以降低其电阻率。

19. 发明授权

US5892269A Semiconductor device including an intrusion film layer 失效
标题翻译：包括侵入膜层的半导体装置
公开(公告)号：US5892269A
公开(公告)日：1999-04-06
申请号：US806425
申请日：1997-02-26
申请人： Yasunori Inoue , Hideki Mizuhara
发明人： Yasunori Inoue , Hideki Mizuhara
IPC分类号： H01L21/265 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/00 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L23/564 , H01L21/3105 , H01L21/76801 , H01L21/76825 , H01L21/76828 , H01L23/5226 , H01L23/53223 , H01L21/76829 , H01L2924/0002
摘要： A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.
摘要翻译：获得包括平坦化和耐水性优异的绝缘膜的半导体器件。在该半导体装置中，在导电层上形成包含杂质的第一绝缘膜。在第一绝缘膜和导电层之间形成膜，用于基本上防止杂质进入导电层。改善了第一绝缘膜的耐水性，因为第一绝缘膜中含有杂质。通过使用平坦化优良的绝缘膜作为第一绝缘膜，可以获得平坦化和耐水性都优异的第一绝缘膜。设置在第一绝缘膜和导电层之间的膜防止第一绝缘膜的杂质进入导电层。因此，可以防止导电层的可靠性的降低。

20. 发明授权

US08378229B2 Circuit board and method for manufacturing semiconductor modules and circuit boards 失效
标题翻译：电路板及制造半导体模块及电路板的方法
公开(公告)号：US08378229B2
公开(公告)日：2013-02-19
申请号：US12813978
申请日：2010-06-11
申请人： Mayumi Nakasato , Hideki Mizuhara
发明人： Mayumi Nakasato , Hideki Mizuhara
IPC分类号： H05K1/11
CPC分类号： H01L23/142 , H01L21/486 , H01L23/49827 , H01L2224/16225 , H05K3/427 , H05K3/445 , H05K2201/0355 , H05K2201/0382 , H05K2201/09827 , H05K2203/0143 , H05K2203/068 , Y10T29/49155
摘要： A circuit board includes a substrate made principally of metal. An opening is provided on the substrate. A first wiring layer is provided on one surface of the substrate via a first insulating layer, and a second wiring layer is provided on the other surface of the substrate via a second insulating layer. A conductor penetrates the substrate via the opening and connects the first wiring layer with the second wiring layer. An end of the opening at one surface side of the substrate has a tapering form on a surface layer thereof, and the first insulating layer has a recess on an upper surface thereof in an upper region of the opening.
摘要翻译：电路板包括主要由金属制成的基板。在基板上设置开口。第一布线层经由第一绝缘层设置在基板的一个表面上，第二布线层经由第二绝缘层设置在基板的另一表面上。导体经由开口穿透基板，并将第一布线层与第二布线层连接。在基板的一个表面侧的开口的端部在其表面层上具有渐缩形状，并且第一绝缘层在开口的上部区域中具有在其上表面上的凹部。

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