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11. 发明申请

US20080030235A1 CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP 有权
标题翻译：基于可编程逻辑的芯片系统的时钟发生器架构
公开(公告)号：US20080030235A1
公开(公告)日：2008-02-07
申请号：US11871741
申请日：2007-10-12
申请人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
发明人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
IPC分类号： H03D9/00
CPC分类号： H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.
摘要翻译：一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。可编程逻辑块耦合到时钟调节电路和实时时钟。

12. 发明申请

US20080007293A1 NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
标题翻译： FPGA的非易失性查看表
公开(公告)号：US20080007293A1
公开(公告)日：2008-01-10
申请号：US11858341
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V CC。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

13. 发明申请

US20080007291A1 NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
公开(公告)号：US20080007291A1
公开(公告)日：2008-01-10
申请号：US11858322
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： H03K19/173
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

14. 发明授权

US07187610B1 Flash/dynamic random access memory field programmable gate array 失效
标题翻译：闪存/动态随机存取存储器现场可编程门阵列
公开(公告)号：US07187610B1
公开(公告)日：2007-03-06
申请号：US11484244
申请日：2006-07-10
申请人： John McCollum , Vidya Bellippady , Gregory Bakker
发明人： John McCollum , Vidya Bellippady , Gregory Bakker
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/404 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C11/4093 , G11C14/00 , G11C14/0018 , G11C16/0441 , G11C16/3431
摘要： A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.
摘要翻译：一种用于提供用于选择性地互连集成电路设备中的N对节点的电路的方法，包括：提供具有多个字线和多个位线的存储器阵列; 提供多个动态随机存取存储器字线; 为集成电路中的每对节点提供单独的开关，每个开关与多个位线之一和多个动态随机存取存储器字线之一的唯一组合相关联，每个开关包括刷新晶体管和开关晶体管 ; 以及提供具有至少N个不同状态的地址解码器，用于向多个字线和多个动态随机存取存储器字线提供信号。

15. 发明申请

US20060284324A1 POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT 有权
标题翻译：用于系统级芯片集成电路的上电和掉电电路
公开(公告)号：US20060284324A1
公开(公告)日：2006-12-21
申请号：US11467279
申请日：2006-08-25
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H01L23/52
CPC分类号： G11C5/147 , H01L2924/0002 , H03K17/22 , Y10T307/50 , Y10T307/724 , H01L2924/00
摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
摘要翻译：用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。第二电压外部耦合到第一I / O焊盘。第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。第四I / O焊盘耦合到电压调节器的反馈输入端。集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。

16. 发明授权

US07138824B1 Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks 有权
标题翻译：集成多功能模拟电路，包括电压，电流和温度监控器以及栅极驱动器电路块
公开(公告)号：US07138824B1
公开(公告)日：2006-11-21
申请号：US11016699
申请日：2004-12-17
申请人： Gregory Bakker , Rabindranath Balasubramanian
发明人： Gregory Bakker , Rabindranath Balasubramanian
IPC分类号： H03H17/16
CPC分类号： H03K19/17732 , H03K17/687
摘要： An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.
摘要翻译：集成多功能模拟电路包括耦合到第一I / O焊盘的至少一个MOSFET栅极驱动电路。至少一个电压感测电路耦合到第二I / O焊盘。至少一个电流感测电路耦合到第二I / O焊盘和第三I / O焊盘。至少一个温度感测电路耦合到第四I / O焊盘。

17. 发明申请

US20060255832A1 NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP 有权
标题翻译：基于可编程逻辑的芯片系统的非易失性存储器架构
公开(公告)号：US20060255832A1
公开(公告)日：2006-11-16
申请号：US11460055
申请日：2006-07-26
申请人： Theodore Speers , Limin Zhu , Kurt Kolkind , Gregory Bakker
发明人： Theodore Speers , Limin Zhu , Kurt Kolkind , Gregory Bakker
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.
摘要翻译：可编程片上系统集成电路器件包括可编程逻辑块。数字输入/输出电路块耦合到可编程逻辑块。 SRAM块耦合到可编程逻辑块。至少一个非易失性存储器块耦合到可编程逻辑块。 JTAG端口耦合到可编程逻辑块。包括模拟 - 数字转换器的模拟电路块可以耦合到可编程逻辑块，并且模拟输入/输出电路块可以耦合到模拟电路块。

18. 发明授权

US07119398B1 Power-up and power-down circuit for system-on-a-chip integrated circuit 有权
标题翻译：用于片上系统集成电路的上电和掉电电路
公开(公告)号：US07119398B1
公开(公告)日：2006-10-10
申请号：US11021092
申请日：2004-12-22
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H02J1/10
CPC分类号： G11C5/147 , H01L2924/0002 , H03K17/22 , Y10T307/50 , Y10T307/724 , H01L2924/00
摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
摘要翻译：用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。第二电压外部耦合到第一I / O焊盘。第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。第四I / O焊盘耦合到电压调节器的反馈输入端。集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。

19. 发明申请

US20060181305A1 INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL 有权
标题翻译：集成电路，包括可编程逻辑和外部器件芯片允许超控
公开(公告)号：US20060181305A1
公开(公告)日：2006-08-17
申请号：US11279046
申请日：2006-04-07
申请人： Rabindranath Balasubramanian , Kurt Kolkind , Gregory Bakker
发明人： Rabindranath Balasubramanian , Kurt Kolkind , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.
摘要翻译：集成电路装置包括可编程逻辑块，监视输入，条件感测电路，耦合到所述监控输入并且被配置为响应于感测所述监视输入处的状况而在输出处产生状态感测信号，第一数字输入，第一数字输出和门控电路，其配置在可编程逻辑块中并耦合在第一数字输入和第一数字输出之间。门控电路具有耦合到条件感测电路并且产生输出的选通输入。在不存在条件感测信号的情况下，该输出与第一数字输入的输入状态相关，并且在条件感测信号存在的情况下采用超驰状态。

20. 发明申请

US20060119385A1 Programmable system on a chip for power-supply voltage and current monitoring and control 有权
公开(公告)号：US20060119385A1
公开(公告)日：2006-06-08
申请号：US11345549
申请日：2006-01-31
申请人： Rabindranath Balasubramanian , Gregory Bakker
发明人： Rabindranath Balasubramanian , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.

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