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11. 发明授权

US06320795B1 Pseudo-static leakage-tolerant register file bit-cell circuit 有权
标题翻译：伪静态容错寄存器文件位单元电路
公开(公告)号：US06320795B1
公开(公告)日：2001-11-20
申请号：US09733225
申请日：2000-12-08
申请人： Ganesh Balamurugan , Ram K. Krishnamurthy
发明人： Ganesh Balamurugan , Ram K. Krishnamurthy
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1051
摘要： A register file for use within, for example, a microprocessor or other digital processing device includes a register file cell having a pull down transistor that is driven by a static logic circuit (e.g., a NOR gate). During a read operation, the static logic circuit causes the pull down transistor to discharge a dynamic bit line node when a predetermined data value is stored within a data storage area of the register file cell. The logic circuit serves to isolate the input terminal of the pull down transistor from a potentially noisy read signal received by the register file cell, thus preventing noise induced leakage currents from being created. In one embodiment, a bias circuit is provided that applies a bias signal to the pull down transistor during non-read intervals to significantly reduce leakage currents flowing through the pull down transistor at these times.
摘要翻译：在例如微处理器或其它数字处理装置中使用的寄存器文件包括具有由静态逻辑电路（例如，或非门）驱动的下拉晶体管的寄存器文件单元。在读取操作期间，当预定数据值存储在寄存器文件单元的数据存储区域内时，静态逻辑电路使下拉晶体管放电动态位线节点。逻辑电路用于将下拉晶体管的输入端与由寄存器堆单元接收的潜在噪声读信号隔离，从而防止产生噪声感应的漏电流。在一个实施例中，提供偏置电路，其在非读取间隔期间向下拉晶体管施加偏置信号，以显着减少在这些时间流过下拉晶体管的漏电流。

12. 发明授权

US08015429B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08015429B2
公开(公告)日：2011-09-06
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H03K9/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

13. 发明申请

US20100164539A1 SYSTEM AND APPARATUS OF RECONFIGURABLE TRANSCEIVER DESIGN FOR MULTI-MODE SIGNALING 有权
标题翻译：用于多模式信号的可重构收发器设计的系统和装置
公开(公告)号：US20100164539A1
公开(公告)日：2010-07-01
申请号：US12347858
申请日：2008-12-31
申请人： Ganesh Balamurugan , Bryan Casper
发明人： Ganesh Balamurugan , Bryan Casper
IPC分类号： H03K17/16
CPC分类号： H03K19/018585
摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.
摘要翻译：对于广泛的I / O系统要求可重新配置的收发器。可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。可以对所有发送模式预先强调要传输的信号。可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

14. 发明授权

US07286006B2 Sign-sign least means square filter 有权
标题翻译：符号最小的意思是方形滤波器
公开(公告)号：US07286006B2
公开(公告)日：2007-10-23
申请号：US10879417
申请日：2004-06-28
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/00
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

15. 发明申请

US20050286623A1 Adaptive filter structure with two adaptation modes 审中-公开
标题翻译：具有两种自适应模式的自适应滤波器结构
公开(公告)号：US20050286623A1
公开(公告)日：2005-12-29
申请号：US10879948
申请日：2004-06-28
申请人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
发明人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
IPC分类号： H03H15/00 , H03H21/00 , H03K5/159 , H04L25/03
CPC分类号： H03H15/00 , H03H21/0001 , H03H2015/007 , H04L25/03038 , H04L2025/03726
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

16. 发明申请

US20210119710A1 OPTICAL COHERENT RECEIVER ON A CHIP 有权
公开(公告)号：US20210119710A1
公开(公告)日：2021-04-22
申请号：US17133360
申请日：2020-12-23
申请人： Meer Nazmus Sakib , Peicheng Liao , Ranjeet Kumar , Duanni Huang , Haisheng Rong , Harel Frish , John Heck , Chaoxuan Ma , Hao Li , Ganesh Balamurugan
发明人： Meer Nazmus Sakib , Peicheng Liao , Ranjeet Kumar , Duanni Huang , Haisheng Rong , Harel Frish , John Heck , Chaoxuan Ma , Hao Li , Ganesh Balamurugan
IPC分类号： H04B10/61
摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.

17. 发明申请

US20190033630A1 POLARIZATION DE-MULTIPLEXING FOR INTENSITY-MODULATED DIRECT-DETECTION (IM-DD) OPTICAL COMMUNICATIONS 审中-公开
公开(公告)号：US20190033630A1
公开(公告)日：2019-01-31
申请号：US15834954
申请日：2017-12-07
申请人： Taehwan Kim , Ganesh Balamurugan , Hao Li , Hasitha Jayatilleka
发明人： Taehwan Kim , Ganesh Balamurugan , Hao Li , Hasitha Jayatilleka
IPC分类号： G02F1/01
摘要： Embodiments include apparatuses, methods, and systems including a dynamic polarization controller (DPC) to receive a first light beam and a second light beam, to adjust a rotation of a state of polarization (SOP) of the first light beam and the second light beam to generate a third light beam and a fourth light beam, under the control of a first control signal, a second control signal, and a third control signal. The first control signal may be related to a phase difference between the third light beam and the fourth light beam, the second control signal may be related to an intensity difference between the third light beam and the fourth light beam, and the third control signal may be related to a rotation of a SOP of the third light beam and the fourth light beam. Other embodiments may also be described and claimed.

18. 发明授权

US09384163B2 Non-linear termination for an on-package input/output architecture 有权
标题翻译：用于封装输入/输出架构的非线性终端
公开(公告)号：US09384163B2
公开(公告)日：2016-07-05
申请号：US13995110
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
IPC分类号： G06F13/40 , G06F13/14 , G06F13/36
CPC分类号： G06F13/4086 , G06F13/14 , G06F13/36 , Y02D10/14 , Y02D10/151
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多个导线的长度匹配。

19. 发明授权

US08375242B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H04L27/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

20. 发明申请

US20110289341A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

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