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11. 发明授权

US06661213B2 On-chip filter-regulator, such as one for a microprocessor phase locked loop (PLL) supply 有权
公开(公告)号：US06661213B2
公开(公告)日：2003-12-09
申请号：US09916926
申请日：2001-07-27
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： G05F156
CPC分类号： G05F1/575 , H03L7/06
摘要： An on-chip, e.g., on a microprocessor, super filter-regulator acts as a voltage regulator and a low-pass filter. The voltage regulator generates a constant DC output voltage and regulates the DC voltage against instantaneous load changes. The low-pass filter and actively filters AC interference out of the DC output voltage. The super filter-regulator provides the filtered and regulated DC voltage to a phase locked loop circuit.

12. 发明授权

US06393089B1 Frequency divider 有权
标题翻译：分频器
公开(公告)号：US06393089B1
公开(公告)日：2002-05-21
申请号：US09671284
申请日：2000-09-27
申请人： Gustavo Maba , Ernest Knoll
发明人： Gustavo Maba , Ernest Knoll
IPC分类号： H03K2100
CPC分类号： H03K23/544
摘要： A frequency divider includes an output-and-control-signals generation circuit. The output-and-control-signals generation circuit outputs an output clock signal and a control signal responsive to an input clock signal and a state signal. A shift register, characterized by having a count-sequence length of 2n−1, outputs the state signal responsive to the output clock signal. A feedback loop is associated with the shift register. An exclusive or (XOR) gate, a multiplexer, and a plurality of flip-flops are disposed within the feedback loop. The multiplexer has a first input and a second input. A parallel-to-serial-input generation circuit is coupled to the output- and control-signals generation circuit and to the shift register, and receives the control signal. The first input of the multiplexer is coupled to the shift register and the second input of the multiplexer is coupled to the parallel-to-serial-input generation circuit.
摘要翻译：分频器包括输出和控制信号发生电路。输出和控制信号产生电路根据输入时钟信号和状态信号输出输出时钟信号和控制信号。具有计数序列长度为2n-1的移位寄存器响应输出时钟信号输出状态信号。反馈回路与移位寄存器相关联。在反馈回路内设置独占或（XOR）门，复用器和多个触发器。多路复用器具有第一输入和第二输入。并行串行输入产生电路耦合到输出和控制信号产生电路和移位寄存器，并接收控制信号。多路复用器的第一输入耦合到移位寄存器，并且多路复用器的第二输入端耦合到并行到串行输入的发生电路。

13. 发明授权

US06313615B1 On-chip filter-regulator for a microprocessor phase locked loop supply 有权
标题翻译：用于微处理器锁相环电路的片上滤波调节器
公开(公告)号：US06313615B1
公开(公告)日：2001-11-06
申请号：US09661138
申请日：2000-09-13
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： G05F156
CPC分类号： G05F1/575 , H03L7/06
摘要： An on-chip, e.g., on a microprocessor, super filter-regulator acts as a voltage regulator and a low-pass filter. The voltage regulator generates a constant DC output voltage and regulates the DC voltage against instantaneous load changes. The low-pass filter and actively filters AC interference out of the DC output voltage. The super filter-regulator provides the filtered and regulated DC voltage to a phase locked loop circuit.
摘要翻译：片上，例如在微处理器上，超滤器调节器用作电压调节器和低通滤波器。电压调节器产生恒定的直流输出电压，并根据瞬时负载变化调节直流电压。低通滤波器主动滤除直流输出电压的交流干扰。超级滤波器调节器将滤波和调节的直流电压提供给锁相环电路。

14. 发明授权

US07605668B2 Delay stage with controllably variable capacitive load 有权
标题翻译：具有可控可变容性负载的延迟级
公开(公告)号：US07605668B2
公开(公告)日：2009-10-20
申请号：US11609819
申请日：2006-12-12
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03B5/24
CPC分类号： H03B5/20 , H03K3/0315 , H03K5/133 , H03K2005/00045 , H03K2005/00071 , H03L7/0995
摘要： Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.
摘要翻译：这里公开的可控可变电容器负载的实施例可以与延迟级或其他元件一起使用，例如在压控振荡器中。

15. 发明授权

US07363523B2 Method and apparatus for controlling power management state transitions 有权
标题翻译：用于控制电源管理状态转换的方法和装置
公开(公告)号：US07363523B2
公开(公告)日：2008-04-22
申请号：US10931565
申请日：2004-08-31
申请人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad M. Dendinger , Jorge P. Rodriguez , Ernest Knoll , David I. Poisner
发明人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad M. Dendinger , Jorge P. Rodriguez , Ernest Knoll , David I. Poisner
IPC分类号： G06F1/32 , G06F1/00 , G01R21/06
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.
摘要翻译：诸如处理器的集成电路器件启动向第一电源管理状态的转变。然后，设备接收到退出第一电源管理状态的请求，并且响应于退出基准工作电压（例如最小工作电压）和当前电压的最高处的第一电源管理状态。一方面，可以使用模数转换器来确定当前的电压电平。此外，对于一个方面，第一电源管理状态可以是更深的睡眠（C 4）状态，并且处理器可以响应于总线事件（例如总线监听）而快速退出到C 2状态。

16. 发明授权

US07265637B2 Startup/yank circuit for self-biased phase-locked loops 有权
标题翻译：启动/匝电路用于自偏置锁相环
公开(公告)号：US07265637B2
公开(公告)日：2007-09-04
申请号：US11476690
申请日：2006-06-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译：用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。在两种操作模式下控制锁相环的方法可以使用上述装置。

17. 发明申请

US20080150596A1 CHARGE PUMP CIRCUIT 审中-公开
标题翻译：充电泵电路
公开(公告)号：US20080150596A1
公开(公告)日：2008-06-26
申请号：US11615753
申请日：2006-12-22
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L2207/06
摘要： Disclosed herein are embodiments of a charge pump that can provide an output voltage with an output current that remains sufficiently constant over an operating range of the output voltage
摘要翻译：这里公开的电荷泵的实施例可以提供输出电压，输出电流在输出电压的工作范围内保持足够恒定

18. 发明申请

US20050206459A1 Startup/yank circuit for self-biased phase-locked loops 有权
公开(公告)号：US20050206459A1
公开(公告)日：2005-09-22
申请号：US11122064
申请日：2005-05-05
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： G01R23/12 , G01R31/02 , H03L7/00 , H03L7/06 , H03L7/089 , H03L7/12 , H03L7/18
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

19. 发明授权

US06894569B2 High-performance charge pump for self-biased phase-locked loop 失效
标题翻译：用于自偏置锁相环的高性能电荷泵
公开(公告)号：US06894569B2
公开(公告)日：2005-05-17
申请号：US10330556
申请日：2002-12-30
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03B5/32 , H03L7/00 , H03L7/089 , H03L7/18
CPC分类号： H03L7/0893 , H03L7/0896 , H03L7/18
摘要： A charge pump includes a charge circuit switch, a pump circuit switch, and a controller for generating a first control signal for switching the charge circuit switch and a second control signal for switching the pump circuit. In order to reduce the effects of self-jitter and improve signal quality, the controller generates the first and second control signals so that they have a same amplitude and slew rate. This results in improving steady-state phase error (DC skew). To further improve performance, current sources of the charge pump are controlled to operate continuously. This advantageously minimizes parastic switching currents. The charge pump may be incorporated within a phase-locked loop for purposes of generating frequency signals. The phase-locked loop may be self-biased. A processing system having, for example, a microprocessor-based computing architecture may advantageously include the phase-locked loop for performing any one of a variety of applications.
摘要翻译：电荷泵包括充电电路开关，泵电路开关和用于产生用于切换充电电路开关的第一控制信号的控制器和用于切换泵电路的第二控制信号。为了减少自抖动的影响并提高信号质量，控制器产生第一和第二控制信号，使它们具有相同的幅度和转换速率。这导致稳态相位误差（DC偏移）的改善。为了进一步提高性能，电流泵的电流源被控制以连续工作。这有利地最小化了临时开关电流。为了产生频率信号的目的，电荷泵可以结合在锁相环内。锁相环可以是自偏置的。具有例如基于微处理器的计算架构的处理系统可以有利地包括用于执行各种应用中的任何一个的锁相环。

20. 发明申请

US20060244542A1 Startup/yank circuit for self-biased phase-locked loops 有权
标题翻译：启动/匝电路用于自偏置锁相环
公开(公告)号：US20060244542A1
公开(公告)日：2006-11-02
申请号：US11476690
申请日：2006-06-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译：用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。在两种操作模式下控制锁相环的方法可以使用上述装置。

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