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11. 发明授权

US07499498B2 Hybrid memory architecture for reduced state sequence estimation (RSSE) techniques 失效
标题翻译：用于缩减状态序列估计（RSSE）技术的混合存储器架构
公开(公告)号：US07499498B2
公开(公告)日：2009-03-03
申请号：US11256182
申请日：2005-10-21
申请人： Kameran Azadet , Erich Franz Haratsch
发明人： Kameran Azadet , Erich Franz Haratsch
IPC分类号： H04L5/12 , H04L23/02
CPC分类号： H04L25/03197 , H04L25/03235 , H04L25/03299
摘要： A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.
摘要翻译：公开了一种用于改进缩减复杂度序列估计技术（例如缩减状态序列估计（RSSE））的处理时间的方法和装置。预先计算RSSE中分支度量值的可能值，以允许流水线化和缩短关键路径。通过分别预先计算多维网格码的每个维度，预先计算的计算负荷被减少用于多维网格码。使用预滤波技术通过缩短信道存储器来降低计算复杂度。公开了一种用于具有长度为L的信道存储器的信道的RSSE的混合存活器存储器架构，其中对应于L个过去的解码周期的幸存者被存储在寄存器交换架构中，并且与随后的解码周期相对应的幸存者被存储在跟踪（TBA）或注册交换架构（REA）。符号被映射到信息位以在从第一寄存器交换架构移动到追溯架构（TBA）或第二寄存器交换架构之前减小字大小。

12. 发明授权

US07380199B2 Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced-state Viterbi detector 有权
标题翻译：用于在精简状态维特比检测器中进行预计算和流水线选择分支度量的方法和装置
公开(公告)号：US07380199B2
公开(公告)日：2008-05-27
申请号：US10853089
申请日：2004-05-25
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H04L25/03235 , G11B20/10296 , H03M13/41
摘要： A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced-state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced-state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.
摘要翻译：公开了一种用于利用本地反馈来提高降维态维特比检测器的最大数据速率的方法和装置。通过预先计算多个候选分支度量并执行适当的分支度量的流水线选择，可以改善所公开的减少状态维特比检测器可以实现的最大数据速率。因此，公开了一种缩减状态维特比检测器，其预先计算一个或多个信道符号的推测序列的分支度量; 基于使用至少两个流水线寄存器的至少一个对应状态的至少一个判定来选择所述预计算分支度量中的一个; 并为给定状态选择具有最佳路径度量的路径。

13. 发明授权

US07363576B2 Method and apparatus for pipelined joint equalization and decoding for gigabit communications 有权
标题翻译：用于千兆通信的流水线联合均衡和解码的方法和装置
公开(公告)号：US07363576B2
公开(公告)日：2008-04-22
申请号：US11234446
申请日：2005-09-26
申请人： Kameran Azadet , Erich Franz Haratsch
发明人： Kameran Azadet , Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/03 , H04L25/03057 , H04L25/03235 , H04L25/4917
摘要： A method and apparatus for the implementation of reduced state sequence estimation is disclosed with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.
摘要翻译：公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行预测）具有增加的吞吐量，相对于先行深度，硬件复杂度只有线性增加。本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

14. 发明授权

US06690754B1 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques 有权
标题翻译：减少状态序列估计（RSSE）技术的计算复杂度和放松关键路径的方法和装置
公开(公告)号：US06690754B1
公开(公告)日：2004-02-10
申请号：US09326785
申请日：1999-06-04
申请人： Erich Franz Haratsch , Harish Viswanathan
发明人： Erich Franz Haratsch , Harish Viswanathan
IPC分类号： H04L100
CPC分类号： H04L25/03235 , H04L25/03197 , H04L25/03299
摘要： A method and apparatus are disclosed for reducing the complexity of reduced state sequence estimation (RSSE) techniques for a given number of states while also reducing the critical path problem. The intersymbol interference due to the less significant tail taps of the channel impulse response is processed with a lower complexity cancellation algorithm using tentative decisions, while the intersymbol interference due to the more significant initial taps is processed with a more complex cancellation algorithm, such as a reduced state sequence estimation technique or an M-algorithm technique. A receiver is disclosed that includes a circuit for processing intersymbol interference due to the less significant tail taps using tentative decisions and an RSSE circuit for processing the intersymbol interference due to the more significant taps.
摘要翻译：公开了一种用于降低给定数量状态的缩减状态序列估计（RSSE）技术的复杂性的方法和装置，同时还减少了关键路径问题。由于采用临时决策的较低复杂度的消除算法，处理信道脉冲响应较不重要的尾部抽头引起的符号间干扰，而采用更为复杂的初始抽头的符号间干扰由更为复杂的消除算法（例如缩减状态序列估计技术或M算法技术。公开了一种接收器，其包括用于使用暂定决定由于使用较不重要的尾部抽头来处理符号间干扰的电路和用于处理由于较重要的抽头引起的符号间干扰的RSSE电路。

15. 发明授权

US08930797B2 Method and apparatus for iterative error-erasure decoding 有权
标题翻译：用于迭代误码解码的方法和装置
公开(公告)号：US08930797B2
公开(公告)日：2015-01-06
申请号：US12533484
申请日：2009-07-31
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H03M13/00 , H03M13/45 , H03M13/15
CPC分类号： H03M13/455 , H03M13/154
摘要： Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.
摘要翻译：提供了改进的迭代误差解码方法和装置。通过获得与该信号相关联的多个符号和一个或多个相应的可靠性值来解码信号; 生成由L个符号构成的至少一个擦除列表和由L'个符号组成的至少一个缩短的擦除列表，其中L'小于L; 以及通过从所述擦除列表和所述缩短删除列表中的至少一个进行擦除来构造擦除集合。还通过使用软输出检测器产生一个或多个可靠性值来处理信号; 通过将可靠性值与至少一个可靠性阈值（或通过排序）进行比较来生成符号擦除列表; 并使用擦除列表执行错误擦除解码。可以选择使用反馈信息来调整擦除列表的大小。

16. 发明申请

US20130223199A1 STORAGE MEDIA INTER-TRACK INTERFERENCE CANCELLATION 有权
标题翻译：存储媒体互联干扰消除
公开(公告)号：US20130223199A1
公开(公告)日：2013-08-29
申请号：US13591980
申请日：2012-08-22
申请人： Timothy B. Lund , Carl E. Forhan , Timothy W. Swatosh , Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park
发明人： Timothy B. Lund , Carl E. Forhan , Timothy W. Swatosh , Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park
IPC分类号： G11B20/10
CPC分类号： G11B20/10046 , G11B5/012 , G11B5/09 , G11B19/045 , G11B20/10268 , G11B20/10398 , G11B20/10462 , G11B20/1407 , G11B2020/183 , G11B2220/2516
摘要： Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads sectors in a desired track of the storage medium. An iterative decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track are read. An ITI canceller of the read channel estimates ITI in the read sectors of the desired track corresponding to the selected sectors of the adjacent track and subtracts the estimated ITI of the adjacent track from the data for the sectors of the desired track, providing updated sector data. The ITI cancelled data is replayed to the iterative decoder, which decodes the ITI cancelled data and provides the decoded ITI cancelled data as output data of the read channel.
摘要翻译：所描述的实施例提供了从存储介质的期望轨迹读取的一个或多个扇区消除轨道间干扰（ITI）的方法。读通道读取存储介质的期望轨道中的扇区。读通道的迭代解码器解码读扇区，并且如果从存储介质错误地恢复读扇区，则读取第一相邻轨道的选定扇区。读通道的ITI消除器估计对应于相邻磁道的所选扇区的期望磁道的读扇区中的ITI，并从期望磁道的扇区的数据中减去相邻磁迹的估计ITI，从而提供更新的扇区数据。 ITI取消的数据被重播到迭代解码器，该解码器对ITI取消的数据进行解码，并将解码的ITI取消的数据作为读取通道的输出数据提供。

17. 发明申请

US20090313531A1 Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths 失效
标题翻译：用于使用多步网格处理接收信号的方法和装置以及用于多个网格路径的选择信号
公开(公告)号：US20090313531A1
公开(公告)日：2009-12-17
申请号：US12547841
申请日：2009-08-26
申请人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
发明人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
IPC分类号： H03M13/25 , G06F11/08
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).
摘要翻译：提供了用于以比常规设计可实现的更高数据速率执行SOVA检测的方法和装置。接收到的信号通过以下步骤来处理：（i）确定至少三个选择信号，其将通过多步网格的多个路径定义到给定状态，其中多条路径中的第一条路径是用于每个单步路段的获胜路径，多步骤格雷周期的网格周期，第二路径是第一单步网格周期的获胜路径，并且是多步骤网格周期的第二单步网格周期的丢失路径，并且第三条路径是第一个单步网格周期的失败之路，是多阶段格雷周期的第二个单步阶段的获胜路径; 和（ii）确定至少一个可靠性值（诸如与通过多步网格的最大似然路径相关联的比特决定的可靠性值或每个多步网格周期的多个可靠性值）。

18. 发明申请

US20090292975A1 METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING 有权
标题翻译：用于迭代错误解码的方法和装置
公开(公告)号：US20090292975A1
公开(公告)日：2009-11-26
申请号：US12533484
申请日：2009-07-31
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H03M13/00 , G06F7/06
CPC分类号： H03M13/455 , H03M13/154
摘要： Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.
摘要翻译：提供了改进的迭代误差解码方法和装置。通过获得与该信号相关联的多个符号和一个或多个相应的可靠性值来解码信号; 生成由L个符号构成的至少一个擦除列表和由L'个符号组成的至少一个缩短的擦除列表，其中L'小于L; 以及通过从所述擦除列表和所述缩短删除列表中的至少一个进行擦除来构造擦除集合。还通过使用软输出检测器产生一个或多个可靠性值来处理信号; 通过将可靠性值与至少一个可靠性阈值（或通过排序）进行比较来生成符号擦除列表; 并使用擦除列表执行错误擦除解码。可以选择使用反馈信息来调整擦除列表的大小。

19. 发明申请

US20080189532A1 METHOD AND APPARATUS FOR PRECOMPUTATION AND PIPELINED SELECTION OF BRANCH METRICS IN A REDUCED STATE VITERBI DETECTOR 失效
标题翻译：用于在降低状态VITERBI检测器中预分配和分配选择分支量度的方法和装置
公开(公告)号：US20080189532A1
公开(公告)日：2008-08-07
申请号：US12101322
申请日：2008-04-11
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： G06F9/32
CPC分类号： H04L25/03235 , G11B20/10296 , H03M13/41
摘要： A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.
摘要翻译：公开了一种用于利用本地反馈来提高降维态维特比检测器的最大数据速率的方法和装置。通过预先计算多个候选分支度量并执行适当的分支度量的流水线选择来改进由公开的减少状态维特比检测器可以实现的最大数据速率。因此，公开了一种缩减状态维特比检测器，其预先计算一个或多个信道符号的推测序列的分支度量; 基于使用至少两个流水线寄存器的至少一个对应状态的至少一个判定来选择所述预计算分支度量中的一个; 并为给定状态选择具有最佳路径度量的路径。

20. 发明授权

US08693119B2 Energy-based inter-track interference cancellation 有权
标题翻译：基于能量的轨道间干扰消除
公开(公告)号：US08693119B2
公开(公告)日：2014-04-08
申请号：US13591888
申请日：2012-08-22
申请人： George Mathew , Erich Franz Haratsch , Jongseung Park , Timothy B. Lund
发明人： George Mathew , Erich Franz Haratsch , Jongseung Park , Timothy B. Lund
IPC分类号： G11B27/36 , G11B5/00
CPC分类号： G11B20/24 , G11B5/012 , G11B19/045 , G11B20/10046 , G11B20/10398 , G11B20/1217 , G11B2020/10759 , G11B2020/1232 , G11B2020/1298 , G11B2220/2516
摘要： Described embodiments cancel inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads one or more sectors in the desired track and generates one or more groups of sample values corresponding to each of the sectors. An ITI canceller estimates an ITI response and an ITI signal for each sample value corresponding to (i) a next adjacent track and (ii) a previous adjacent track. If the estimated ITI response of the previous adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the previous adjacent track from each associated sample value of the desired track. If the estimated ITI response of the next adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the next adjacent track from each associated sample value of the desired track.
摘要翻译：所描述的实施例从从存储介质的期望轨道读取的一个或多个扇区中消除轨道间干扰（ITI）。读通道读取所需轨道中的一个或多个扇区，并生成与每个扇区对应的一组或多组样本值。 ITI消除器估计对应于（i）下一个相邻轨道和（ii）先前相邻轨道的每个采样值的ITI响应和ITI信号。如果先前相邻轨道的估计ITI响应达到预定阈值，则ITI消除器从期望轨道的每个相关联采样值中减去对应于先前相邻轨道的估计ITI信号。如果下一相邻轨道的估计ITI响应达到预定阈值，则ITI消除器从期望轨道的每个相关联采样值中减去对应于下一相邻轨道的估计ITI信号。

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