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11. 发明申请

WO2005008747A2 METHODS AND SYSTEMS FOR INSPECTION OF WAFERS AND RETICLES USING DESIGNER INTENT DATA 审中-公开
标题翻译：使用设计者目的数据检验晶片和晶片的方法和系统
公开(公告)号：WO2005008747A2
公开(公告)日：2005-01-27
申请号：PCT/US2004/021459
申请日：2004-07-02
申请人： KLA-TENCOR TECHNOLOGIES , MARELLA, Paul Frank , MCCAULEY, Sharon , CHANG, Ellis , VOLK, William , WILEY, James , WATSON, Sterling , KEKARE, Sagar A. , HESS, Carl
发明人： MARELLA, Paul Frank , MCCAULEY, Sharon , CHANG, Ellis , VOLK, William , WILEY, James , WATSON, Sterling , KEKARE, Sagar A. , HESS, Carl
IPC分类号： H01L21/00
CPC分类号： G06T7/0006 , G01N21/9501 , G01N21/956 , G01N2021/95676 , G03F1/84 , G03F7/7065 , G06T7/0008 , G06T2207/30148
摘要： Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
摘要翻译：提供了使用设计者意图数据检查晶片和分划板的方法和系统。一种计算机实现的方法包括基于通过检查标线产生的检查数据来识别晶片上的滋扰缺陷，所述标线用于在检查晶片之前在晶片上形成图案。另一种计算机实现的方法包括通过结合表示掩模版的数据分析通过检查晶片产生的数据来检测晶片上的缺陷，其包括识别掩模版的不同类型部分的标记。另外的计算机实现的方法包括基于改变晶片上形成的器件的特性的缺陷来确定用于处理晶片的制造工艺的特性。其他计算机实现的方法包括基于通过检查晶片产生的数据改变或模拟集成电路设计的一个或多个特性。

12. 发明申请

WO2012170477A3 USING THREE-DIMENSIONAL REPRESENTATIONS FOR DEFECT-RELATED APPLICATIONS 审中-公开
标题翻译：使用缺陷相关应用的三维表示法
公开(公告)号：WO2012170477A3
公开(公告)日：2013-04-25
申请号：PCT/US2012041019
申请日：2012-06-06
申请人： KLA TENCOR CORP , PARK ALLEN , CHANG ELLIS , AJI PRASHANT A , LANGE STEVEN R
发明人： PARK ALLEN , CHANG ELLIS , AJI PRASHANT A , LANGE STEVEN R
IPC分类号： H01L21/66
CPC分类号： G06F17/5068 , G01N21/9501 , G06F17/50 , G06F17/5009 , G06F2217/12 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method for determining one or more inspection parameters for a wafer inspection recipe is described. The method comprises the steps of: generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. The method is performed by a computer system.
摘要翻译：描述了一种用于确定晶片检查配方的一个或多个检查参数的方法。该方法包括以下步骤：基于设计数据生成晶片的一层或多层的三维表示; 以及基于所述三维表示确定用于晶片检查配方的一个或多个检查参数。该方法由计算机系统执行。

13. 发明申请

WO2012016243A8 REGION BASED VIRTUAL FOURIER FILTER 审中-公开
标题翻译：基于区域的虚拟傅里叶滤波器
公开(公告)号：WO2012016243A8
公开(公告)日：2012-09-27
申请号：PCT/US2011046154
申请日：2011-08-01
申请人： KLA TENCOR CORP , GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
发明人： GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
IPC分类号： G06T7/60
CPC分类号： G06T7/001 , G06T2207/10061 , G06T2207/20021 , G06T2207/20056 , G06T2207/30148
摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.
摘要翻译：本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅里叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集合，定义VFF训练使用初始图像数据集合在VFF工作区域的所识别图案化区域内的块，其中每个VFF训练块被定义为涵盖显示选定重复图案的所识别图案化区域的一部分，计算每个VFF训练块的初始光谱利用来自VFF训练块的初始图像数据集，并且通过识别在频域中具有最大值的初始频谱的频率来为每个训练块生成VFF，其中VFF被配置为使得初始频谱的幅度在确定频率显示频谱最大值。

14. 发明申请

WO2011085255A2 INSPECTION GUIDED OVERLAY METROLOGY 审中-公开
标题翻译：检验指导覆盖计量
公开(公告)号：WO2011085255A2
公开(公告)日：2011-07-14
申请号：PCT/US2011/020587
申请日：2011-01-07
申请人： KLA-TENCOR CORPORATION , CHANG, Ellis , WIDMANN, Amir , PARK, Allen
发明人： CHANG, Ellis , WIDMANN, Amir , PARK, Allen
IPC分类号： H01L21/66
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
摘要翻译：检查引导覆盖测量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，识别生成的内部缺陷通过对每个所产生的护理区域执行检查扫描，其中所述检查扫描包括低阈值或高灵敏度检查扫描，识别所述半导体晶片的所述预定图案的重叠部位，所述重叠部位的测量重叠误差大于使用缺陷检查技术选择重叠指定;将所生成的护理区域的所识别的缺陷的位置数据与所生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中所述缺陷接近所识别的一个或多个位置覆盖网站，并基于识别的l生成计量抽样计划 ocations。

15. 发明申请

WO2010014609A2 COMPUTER-IMPLEMENTED METHODS, COMPUTER-READABLE MEDIA, AND SYSTEMS FOR CLASSIFYING DEFECTS DETECTED IN A MEMORY DEVICE AREA ON A WAFER 审中-公开
标题翻译：计算机实现方法，计算机可读介质和用于分类在WAFER中的存储器设备区域中检测到的缺陷的系统
公开(公告)号：WO2010014609A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/051961
申请日：2009-07-28
申请人： KLA-TENCOR CORPORATION , CHOI, SunYong , PAE, YeonHo , CHANG, Ellis
发明人： CHOI, SunYong , PAE, YeonHo , CHANG, Ellis
IPC分类号： G06F19/00 , G06F11/00
CPC分类号： G11C29/56 , G11C29/56008
摘要： Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.
摘要翻译：提供了计算机实现的方法，计算机可读介质和用于分类在晶片上的存储器件区域中检测到的缺陷的系统。

16. 发明申请

WO2007120279A3 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA 审中-公开
标题翻译：与检验数据组合使用设计数据的方法和系统
公开(公告)号：WO2007120279A3
公开(公告)日：2008-11-20
申请号：PCT/US2006061112
申请日：2006-11-20
申请人： KLA TENCOR TECH CORP , ZAFAR KHURRAM , KEKARE SAGAR , CHANG ELLIS , PARK ALLEN , ROSE PETER
发明人： ZAFAR KHURRAM , KEKARE SAGAR , CHANG ELLIS , PARK ALLEN , ROSE PETER
IPC分类号： G06K9/00 , G06K9/62
CPC分类号： G01N21/9501 , G01N2021/8854 , G01R31/31718 , G06T7/001 , G06T2207/30148 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
摘要翻译：提供了与检测数据结合使用设计数据的各种方法和系统。用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。此外，该方法包括将组中的缺陷合并，使得接近每个组中的缺陷位置的设计数据的部分至少相似。该方法还包括将合并步骤的结果存储在存储介质中。

17. 发明申请

WO2008036827A2 METHOD FOR GENERATING A DESIGN RULE MAP HAVING SPATIALLY VARYING OVERLAY BUDGET 审中-公开
标题翻译：用于生成具有空间变化的覆盖预算的设计规则地图的方法
公开(公告)号：WO2008036827A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/079053
申请日：2007-09-20
申请人： KLA-TENCOR TECHNOLOGIES CORPORATION , ADEL, Michael , CHANG, Ellis
发明人： ADEL, Michael , CHANG, Ellis
IPC分类号： G06F17/50
CPC分类号： G03F7/70633 , G03F7/70533
摘要： The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.
摘要翻译：本发明是一种用于生成具有空间变化的重叠误差预算的设计规则图的方法。此外，可以采用空间上可变的重叠误差预算来确定晶片是否符合规格制造。在一种方法中，使用设计规则处理包含制造过程信息和掩模版信息的设计数据文件，以获得具有空间上变化的重叠误差预算的设计图，该设计图定义了设计图上不同空间位置的重叠误差的局部容差。这种空间上可变的重叠误差预算可用于配置晶片。例如，将从制造的晶片上的测量的测量目标获得的覆盖信息与空间上变化的重叠误差预算进行比较，以确定晶片覆盖是否满足要求的规范。

18. 发明申请

WO2012016243A3 REGION BASED VIRTUAL FOURIER FILTER 审中-公开
标题翻译：基于区域的虚拟FOURIER过滤器
公开(公告)号：WO2012016243A3
公开(公告)日：2013-08-15
申请号：PCT/US2011046154
申请日：2011-08-01
申请人： KLA TENCOR CORP , GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
发明人： GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
IPC分类号： H01L21/66 , G06K9/00
CPC分类号： G06T7/001 , G06T2207/10061 , G06T2207/20021 , G06T2207/20056 , G06T2207/30148
摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.
摘要翻译：本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅立叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集，定义VFF训练利用初始的图像数据集，在VFF工作区域的所识别的图案化区域内的块，其中每个VFF训练块被定义为包含所识别的图案化区域的一部分，显示所选择的重复模式，计算每个VFF训练块的初始频谱利用来自VFF训练块的初始图像数据组，以及通过识别在频域中具有最大值的初始频谱的频率，为每个训练块生成VFF，其中VFF被配置为在识别出显示频谱最大值的频率。

19. 发明申请

WO2012016243A2 REGION BASED VIRTUAL FOURIER FILTER 审中-公开
标题翻译：基于区域的虚拟FOURIER过滤器
公开(公告)号：WO2012016243A2
公开(公告)日：2012-02-02
申请号：PCT/US2011/046154
申请日：2011-08-01
申请人： KLA-TENCOR CORPORATION , GAO, Lisheng , WU, Kenong , PARK, Allen , CHANG, Ellis , ZAFAR, Khurram , HUANG, Junqing (Jenny) , GU, Ping , MAHER, Christopher , CHEN, Grace, H. , ROGN, Songnian , WU, Liu-Ming
发明人： GAO, Lisheng , WU, Kenong , PARK, Allen , CHANG, Ellis , ZAFAR, Khurram , HUANG, Junqing (Jenny) , GU, Ping , MAHER, Christopher , CHEN, Grace, H. , ROGN, Songnian , WU, Liu-Ming
IPC分类号： G06T7/60
CPC分类号： G06T7/001 , G06T2207/10061 , G06T2207/20021 , G06T2207/20056 , G06T2207/30148
摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.
摘要翻译：本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅立叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集，定义VFF训练利用初始图像数据组，VFF工作区域的所识别的图案化区域内的块，其中每个VFF训练块被定义为包含所识别的图案化区域的一部分，显示所选择的重复模式，计算每个VFF训练块的初始频谱利用来自VFF训练块的初始图像数据组，以及通过识别在频域中具有最大值的初始频谱的频率，为每个训练块生成VFF，其中VFF被配置为在识别出显示频谱最大值的频率。

20. 发明申请

WO2011085255A3 INSPECTION GUIDED OVERLAY METROLOGY 审中-公开
标题翻译：检查指导覆盖度量
公开(公告)号：WO2011085255A3
公开(公告)日：2011-11-10
申请号：PCT/US2011020587
申请日：2011-01-07
申请人： KLA TENCOR CORP , CHANG ELLIS , WIDMANN AMIR , PARK ALLEN
发明人： CHANG ELLIS , WIDMANN AMIR , PARK ALLEN
IPC分类号： H01L21/66
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
摘要翻译：检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，通过执行检查扫描来检查所产生的护理区域内的缺陷每个生成的护理区域，其中检查扫描包括低阈值或高灵敏度检查扫描，识别具有大于使用缺陷检查技术的所选覆盖规格的测量覆盖误差的半导体晶片的预定图案的覆盖位置将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置，以及生成计量取样基于确定的位置进行计划。

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