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11. 发明授权

US07739498B2 Method and apparatus for multi-table accessing of input/output devices using target security 有权
标题翻译：使用目标安全性对输入/输出设备进行多表访问的方法和装置
公开(公告)号：US07739498B2
公开(公告)日：2010-06-15
申请号：US10047188
申请日：2002-01-15
申请人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
发明人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
IPC分类号： H04L9/32
CPC分类号： G06F12/1491
摘要： A method and an apparatus for performing an I/O device access using targeted security. A software object is executed. A security level for the software object is established. A multi-table input/output (I/O) space access is performed using at least one of the security levels. The function of the object is executed.
摘要翻译：一种使用目标安全性执行I / O设备访问的方法和装置。执行软件对象。建立软件对象的安全级别。使用至少一个安全级别来执行多表输入/输出（I / O）空间访问。执行对象的功能。

12. 发明授权

US07426644B1 System and method for handling device accesses to a memory providing increased memory access security 有权
标题翻译：用于处理对存储器的设备访问的系统和方法，其提供增加的存储器访问安全性
公开(公告)号：US07426644B1
公开(公告)日：2008-09-16
申请号：US10011151
申请日：2001-12-05
申请人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
发明人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
IPC分类号： G06F21/00 , G06F21/22
CPC分类号： G06F12/1441 , G06F12/1491
摘要： A host bridge is described including a memory controller and a security check unit. The memory controller is adapted for coupling to a memory storing data arranged within a multiple memory pages. The memory controller receives memory access signals (e.g., during a memory access), and responds to the memory access signals by accessing the memory. The security check unit receives the memory access signals, wherein the memory access signals convey a physical address within a target memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the target memory page. The security check unit provides the memory access signals to the memory controller dependent upon the security attribute of the target memory page. A computer system is described including a memory storing data arranged within a multiple memory pages, a device operably coupled to the memory and configurable to produce memory access signals, the above described host bridge. The computer system may have, for example, a central processing unit (CPU) including a memory management unit (MMU) operably coupled to the memory and configured to manage the memory. The memory management unit (MMU) may manage the memory such that the memory stores the data arranged within the multiple memory pages. A method is disclosed for providing access security for a memory used to store data arranged within a multiple memory pages.
摘要翻译：描述了主桥，包括存储器控制器和安全检查单元。存储器控制器适于耦合到存储多个存储器页中布置的数据的存储器。存储器控制器接收存储器访问信号（例如，在存储器访问期间），并且通过访问存储器来响应存储器访问信号。安全检查单元接收存储器访问信号，其中存储器访问信号传达目标存储器页面内的物理地址。安全检查单元使用物理地址访问位于存储器中的一个或多个安全属性数据结构，以获得目标存储器页面的安全属性。安全检查单元根据目标存储器页面的安全属性向存储器控制器提供存储器访问信号。描述了一种计算机系统，包括存储布置在多个存储器页内的数据的存储器，可操作地耦合到存储器并且可配置为产生存储器访问信号的设备，上述主机桥。计算机系统可以具有例如包括可操作地耦合到存储器并被配置为管理存储器的存储器管理单元（MMU）的中央处理单元（CPU）。存储器管理单元（MMU）可以管理存储器，使得存储器存储布置在多个存储器页面中的数据。公开了一种用于提供用于存储布置在多个存储器页内的数据的存储器的访问安全性的方法。

13. 发明授权

US07325250B1 Method and apparatus for preventing radio communication system access by an unauthorized modem 失效
标题翻译：用于防止未经授权的调制解调器的无线电通信系统接入的方法和装置
公开(公告)号：US07325250B1
公开(公告)日：2008-01-29
申请号：US09901421
申请日：2001-07-09
申请人： Michael Barclay , Brian C. Barnes , Terry L. Cole , Rodney Schmidt , David W. Smith , Geoffrey S. Strongin
发明人： Michael Barclay , Brian C. Barnes , Terry L. Cole , Rodney Schmidt , David W. Smith , Geoffrey S. Strongin
IPC分类号： G06F17/00 , H04L9/00 , H04L1/00 , H04M1/66 , H04B7/00 , H04B1/02
CPC分类号： H04W12/08 , H04W92/10
摘要： A method and apparatus for preventing radio communication system access by an unauthorized modem. The apparatus comprises a signal detector that determines if an authorization signal has been received from the base station within a specified period of time. The authorization signal authorizes the apparatus to communicate with the base station. A transmitter transmits information to the base station, and a controller disables the transmitter of the apparatus providing that the authorization signal has not been received within the specified period of time.
摘要翻译：一种用于防止未经授权的调制解调器接入无线电通信系统的方法和装置。该装置包括信号检测器，该信号检测器确定在指定的时间段内是否已经从基站接收到授权信号。授权信号授权设备与基站进行通信。发射机向基站发送信息，并且控制器禁止设备的发射机，只要在指定的时间段内没有接收到授权信号。

14. 发明授权

US06378023B1 Interrupt descriptor cache for a microprocessor 失效
标题翻译：微处理器的中断描述符缓存
公开(公告)号：US06378023B1
公开(公告)日：2002-04-23
申请号：US09481005
申请日：2000-01-10
申请人： David S. Christie , Brian C. Barnes
发明人： David S. Christie , Brian C. Barnes
IPC分类号： G06F1324
CPC分类号： G06F13/24 , G06F12/0875
摘要： An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.
摘要翻译：提供了一种用于微处理器的中断描述符缓存器，其被配置为存储与多个中断向量相关联的中断信息。在从计算机系统的主存储器获取中断信息之前，微处理器搜索中断描述符缓存。如果中断信息存储在其中，则中断服务程序的地址由存储的中断信息形成，而不是从主存储器取出中断信息。中断描述符缓存另外被配置为对存储在其中的中断信息的更新的监控存储器访问。如果更新存储中断信息的存储器位置，则中断描述符缓存使存储信息的任何存储位置无效。

15. 发明授权

US5727227A Interrupt coprocessor configured to process interrupts in a computer system 失效
标题翻译：中断协处理器配置为处理计算机系统中的中断
公开(公告)号：US5727227A
公开(公告)日：1998-03-10
申请号：US559659
申请日：1995-11-20
申请人： Rodney W. Schmidt , Brian C. Barnes
发明人： Rodney W. Schmidt , Brian C. Barnes
IPC分类号： G06F9/38 , G06F9/46 , G06F13/24 , G06F1/00
CPC分类号： G06F13/24 , G06F9/3879 , G06F9/462
摘要： A computer system employing an interrupt coprocessor is provided. The interrupt coprocessor is signaled by an interrupt controller to service a particular interrupt request. The interrupt coprocessor may include limited functionality, such that if a particular interrupt request is beyond the capabilities of the interrupt coprocessor, the microprocessor is interrupted. Context saves may be avoided in the interrupt coprocessor. Interrupt latency is reduced, as well as interruption of one or more main microprocessors in the computer system. Several embodiments are shown with a range of interrupt servicing capabilities. A data pump is shown, which is configured to transfer data from a source to a destination. A microcontroller is shown, which may manipulate the data as it is moved from source to destination or access the interrupting device to determine the service needed. Finally, a microprocessor similar to the main microprocessors of the computer system is shown. The microprocessor is capable of accessing system resources in a similar fashion to the main microprocessor, and therefore is capable of performing all interrupt servicing functions.
摘要翻译：提供了一种采用中断协处理器的计算机系统。中断协处理器由中断控制器发出信号，以服务于特定的中断请求。中断协处理器可以包括有限的功能，使得如果特定中断请求超出了中断协处理器的能力，则微处理器被中断。在中断协处理器中可以避免上下文保存。中断延迟减少，以及计算机系统中一个或多个主要微处理器的中断。示出了具有一定范围的中断服务能力的几个实施例。示出了数据泵，其被配置为将数据从源传送到目的地。示出了微控制器，其可以在数据从源移动到目的地时操纵数据，或者访问中断设备以确定所需的服务。最后，显示了类似于计算机系统的主要微处理器的微处理器。微处理器能够以与主微处理器相似的方式访问系统资源，因此能够执行所有中断服务功能。

16. 发明授权

US5280621A Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor 失效
标题翻译：具有通过系统控制处理器与CPU互连的外围设备的专用处理器的个人计算机
公开(公告)号：US5280621A
公开(公告)日：1994-01-18
申请号：US19997
申请日：1993-02-17
申请人： Brian C. Barnes , Mark J. Foster , Lloyd W. Gauthier , Saifee Fakhruddin , David J. DeLisle , David R. Veit
发明人： Brian C. Barnes , Mark J. Foster , Lloyd W. Gauthier , Saifee Fakhruddin , David J. DeLisle , David R. Veit
IPC分类号： G06F13/12
CPC分类号： G06F13/124
摘要： A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.
摘要翻译：多个处理器形成用于与一个或多个外围设备和系统控制处理器进行通信的网络。一个处理器专用于至少一个外围设备。由于系统控制处理器不会与外围设备相对较慢的通信协议负担，因此可以自由地执行其他任务，从而提高整个系统的性能。专用处理器之间的通信协议允许本地和全球通信。

17. 发明授权

US07865948B1 Method and apparatus for restricted execution of security sensitive instructions 有权
标题翻译：用于限制执行安全敏感指令的方法和装置
公开(公告)号：US07865948B1
公开(公告)日：2011-01-04
申请号：US10005248
申请日：2001-12-03
申请人： Brian C. Barnes , Rodney W. Schmidt , Geoffrey S. Strongin
发明人： Brian C. Barnes , Rodney W. Schmidt , Geoffrey S. Strongin
IPC分类号： H04L29/06 , G06F21/00
CPC分类号： G06F9/30145 , G06F9/30181 , G06F21/52 , G06F21/53 , G06F21/54 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： A method and apparatus for restricting the execution of security sensitive instructions. A first security identification (ID) is associated with each of a plurality of instructions or a set of instructions that are to be executed by a processor. Software code running on the processor requests to execute at least one of the plurality of instructions or set of instructions. The processor obtains a second security ID associated with the software code running thereon and compares the second security ID with the first security ID. The processor executes the requested instruction or set of instructions providing that the second security ID matches the first security ID.
摘要翻译：一种限制安全敏感指令执行的方法和装置。第一安全标识（ID）与要由处理器执行的多个指令或一组指令中的每一个相关联。在处理器上运行的软件代码请求执行多个指令或指令集中的至少一个。处理器获得与其上运行的软件代码相关联的第二安全ID，并将第二安全ID与第一安全ID进行比较。处理器执行请求的指令或指令集，条件是第二安全ID与第一安全ID相匹配。

18. 发明授权

US07451324B2 Secure execution mode exceptions 有权
标题翻译：安全执行模式例外
公开(公告)号：US07451324B2
公开(公告)日：2008-11-11
申请号：US10161500
申请日：2002-05-31
申请人： Rodney W. Schmidt , Brian C. Barnes , Geoffrey S. Strongin , David S. Christie
发明人： Rodney W. Schmidt , Brian C. Barnes , Geoffrey S. Strongin , David S. Christie
IPC分类号： G06F21/22
CPC分类号： G06F21/53 , G06F21/71 , G06F2221/2153
摘要： A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack frame, and executing a plurality of security exception instructions.
摘要翻译：一种处理安全异常的方法和系统。该方法包括在基地址的安全存储器中创建安全异常堆栈帧。该方法还包括将故障代码序列地址和一个或多个寄存器值写入到安全异常堆栈帧中，以及执行多个安全异常指令。

19. 发明授权

US06854039B1 Memory management system and method providing increased memory access security 失效
标题翻译：内存管理系统和方法提供更高的内存访问安全性
公开(公告)号：US06854039B1
公开(公告)日：2005-02-08
申请号：US10005271
申请日：2001-12-05
申请人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
发明人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/145 , G06F12/1491
摘要： A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a multiple memory pages. The memory management unit includes a security check receiving a physical address within a selected memory page, and security attributes of the selected memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page. The security check unit generates a fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page. The security attributes of the selected memory page may include a user/supervisor (U/S) bit and a read/write (R/W) bit as defined by the ×86 processor architecture. The one or more security attribute data structures may include a security attribute table directory and one or more security attribute tables. The security attribute table directory may include multiple entries, and each entry of the security attribute table directory may include a present bit and a security attribute table base address field. A central processing unit (CPU) is described including the memory management unit (MMU), and a computer system is disclosed including the CPU. A method is described for providing access security for a memory used to store data arranged within multiple memory pages.
摘要翻译：公开了一种用于管理存储多个存储器页中布置的数据的存储器管理单元（MMU）。存储器管理单元包括接收所选存储器页面内的物理地址的安全检查以及所选存储器页的安全属性。安全检查单元使用物理地址来访问位于存储器中的一个或多个安全属性数据结构，以获得所选存储器页的附加安全属性。安全检查单元根据所选择的存储器页面的安全属性和所选择的存储器页面的附加安全属性生成故障信号。所选存储器页面的安全属性可以包括由x86处理器架构定义的用户/管理器（U / S）位和读/写（R / W）位。一个或多个安全属性数据结构可以包括安全属性表目录和一个或多个安全属性表。安全属性表目录可以包括多个条目，并且安全属性表目录的每个条目可以包括当前位和安全属性表基地址字段。描述了包括存储器管理单元（MMU）的中央处理单元（CPU），并且公开了包括CPU的计算机系统。描述了一种用于提供用于存储布置在多个存储器页内的数据的存储器的访问安全性的方法。

20. 发明授权

US06205467B1 Microprocessor having a context save unit for saving context independent from interrupt requests 失效
标题翻译：微处理器具有上下文保存单元，用于独立于中断请求来保存上下文
公开(公告)号：US06205467B1
公开(公告)日：2001-03-20
申请号：US08557312
申请日：1995-11-14
申请人： J. Andrew Lambrecht , Brian C. Barnes
发明人： J. Andrew Lambrecht , Brian C. Barnes
IPC分类号： G06F900
CPC分类号： G06F9/3863 , G06F9/461
摘要： A microprocessor including a context save unit is provided. The context save unit is configured to periodically perform context saves. When the microprocessor receives an interrupt signal, the microprocessor enters the interrupt service routine without performing a context save. After completing execution of the interrupt service routine, the microprocessor restores the most recently saved context and begins executing the task at that saved context. The interrupt service routine is entered rapidly but the interrupt service routine does not include instructions for saving the registers which it utilizes to perform its function. The context save unit is configured to perform a context save at the occurrence of a variety of events. A fixed or variable time interval may be selected, and each interval includes several options.
摘要翻译：提供了包括上下文保存单元的微处理器。上下文保存单元配置为定期执行上下文保存。当微处理器接收到中断信号时，微处理器进入中断服务程序，而不执行上下文保存。完成中断服务程序的执行后，微处理器恢复最近保存的上下文，并开始在保存的上下文中执行任务。快速进入中断服务程序，但中断服务程序不包含用于保存用于执行其功能的寄存器的指令。上下文保存单元被配置为在发生各种事件时执行上下文保存。可以选择固定或可变时间间隔，并且每个间隔包括若干选项。

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