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11. 发明授权

US08512582B2 Methods of patterning a substrate 有权
标题翻译：图案化衬底的方法
公开(公告)号：US08512582B2
公开(公告)日：2013-08-20
申请号：US12210797
申请日：2008-09-15
申请人： Mark Kiehlbauch , Brett W. Busch , Tuman Earl Allen
发明人： Mark Kiehlbauch , Brett W. Busch , Tuman Earl Allen
IPC分类号： B44C1/22
CPC分类号： H01L21/31144 , H01L21/0337 , H01L27/0207 , H01L27/10852 , H01L28/91
摘要： A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.
摘要翻译：根据本发明的实施例的图案化基板的方法包括在光致抗蚀剂和无定形碳中的至少一个中形成多个开口。这些开口相对于彼此具有共同的最外横截面形状。开口的个体具有至少一个横向开放尺寸，其具有多个之间的变化程度。具有多个开口的光致抗蚀剂暴露于/等离子体处理，其有效地增加了开口的侧向开口尺寸，并且至少减小了开口中所述至少一个开口尺寸的变化程度。考虑了其他方面和实现。

12. 发明授权

US08030168B2 Methods of forming DRAM memory cells 有权
标题翻译：形成DRAM存储单元的方法
公开(公告)号：US08030168B2
公开(公告)日：2011-10-04
申请号：US12419014
申请日：2009-04-06
申请人： Brett W. Busch , David K. Hwang , F. Daniel Gealy
发明人： Brett W. Busch , David K. Hwang , F. Daniel Gealy
IPC分类号： H01L21/8242
CPC分类号： H01L21/76879 , B82Y10/00 , H01L21/28525 , H01L21/76885 , H01L21/76897 , H01L27/10811 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L28/91 , Y10S977/773
摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.
摘要翻译：本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。纳米晶须从第一导电表面生长，并被提供为导电的。提供关于纳米晶须的电绝缘材料。导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。考虑了其他方面和实现。

13. 发明授权

US07413952B2 Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate 失效
标题翻译：形成多个电路部件的方法和形成在基板上方悬垂的多个结构的方法
公开(公告)号：US07413952B2
公开(公告)日：2008-08-19
申请号：US11646051
申请日：2006-12-26
申请人： Brett W. Busch , Fred D. Fishburn , James Rominger
发明人： Brett W. Busch , Fred D. Fishburn , James Rominger
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10852
摘要： A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material. Then, the sacrificial retaining structure is removed from the substrate, and then capacitor dielectric material and conductive second capacitor electrode material are formed over the outer sidewall surfaces of the first capacitor electrode material formed within the first and second sets of capacitor openings.
摘要翻译：在电容器电极形成材料内形成多个电容器电极开口。第一组开口形成为在电容器电极形成材料内比第二组开口更大的深度。在其中形成导电的第一电容器电极材料。牺牲保持结构在第一电容器电极材料和电容器电极形成材料两者之上形成高度，从而使一些电容器电极形成材料暴露。在保持结构就位的情况下，有效地暴露出第一电容器电极材料的外侧壁表面的至少一些电容器电极形成材料被从衬底上蚀刻。然后，从衬底去除牺牲保持结构，然后在形成在第一组和第二组电容器开口内的第一电容器电极材料的外侧壁表面上形成电容器电介质材料和导电的第二电容器电极材料。

14. 发明授权

US07153778B2 Methods of forming openings, and methods of forming container capacitors 有权
公开(公告)号：US07153778B2
公开(公告)日：2006-12-26
申请号：US10783843
申请日：2004-02-20
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

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