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11. 发明申请

US20060112393A1 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US20060112393A1
公开(公告)日：2006-05-25
申请号：US11322378
申请日：2006-01-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

12. 发明授权

US06993035B2 System for routing data packets through a crossbar switch in expansion mode 有权
公开(公告)号：US06993035B2
公开(公告)日：2006-01-31
申请号：US09683231
申请日：2001-12-04
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/46 , H04L49/1576 , H04L49/255 , H04L49/455 , H04L2012/5674
摘要： The present invention describes a switching module for use either in port or speed expansion mode. The switching module is preferably used in a data transmission system consisting of a number of Local Area Networks LANs interconnected by a hub which includes a number of LAN adapters respectively connected to said LANs. A crossbar switch interconnects all LAN adapters and consists of switching modules having first receiving means for storing a first number of data packets; second receiving means for storing a second number of data packets; first outputting means for outputting a first subset of the first number of data packets and the second number of data packets; second outputting means for outputting a second subset of the first number of data packets; and switching means, coupled to the first and second receiving means and coupled to the first and second outputting means for routing the first and the second subsets of the first number of data packets and the second number of data packets to the respective first or second output means. The routing of the incoming data packets to their final destination is done without modifying the data packet header as a data packet sent by a source of adapter contains in its header the physical address of the destination adapter.

13. 发明授权

US06950429B2 IP data transmission network using a route selection based on level 4/5 protocol information 失效
标题翻译： IP数据传输网使用基于4/5协议信息的路由选择
公开(公告)号：US06950429B2
公开(公告)日：2005-09-27
申请号：US09838406
申请日：2001-04-19
申请人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
发明人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
IPC分类号： H04L12/931 , H04L12/935 , H04L12/947 , H04L12/56
CPC分类号： H04L49/602 , H04L49/25 , H04L49/3009
摘要： Data transmission system for transmitting packets of data from a source workstation (10) to a destination workstation (18) wherein the packets of data are transmitted over at least an IP network (14) between an ingress node (16) connected to the source workstation and an egress node (20) connected to the destination workstation, wherein each router within the intermediary nodes along the data path from the ingress node to the egress node determines the best route in a routing table defined by the contents of a field contained in each packet of data being received. For this, the router of the ingress node comprises a configuration table which defines the contents of the TOS field in function of information associated with the 4/5 level protocol such as TCP or UDP.
摘要翻译：用于将数据分组从源工作站（10）发送到目的地工作站（18）的数据传输系统，其中数据分组通过至少一个IP网络（14）在连接到源工作站的入口节点（16）之间传输以及连接到目的地工作站的出口节点（20），其中沿着从入口节点到出口节点的数据路径的中间节点内的每个路由器确定由每个中包含的字段的内容定义的路由表中的最佳路由收到的数据包。为此，入口节点的路由器包括配置表，该配置表根据与诸如TCP或UDP的4/5级协议相关联的信息来定义TOS字段的内容。

14. 发明授权

US06789130B1 Automatic rate adaptation system in a local area network 失效
标题翻译：局域网自动速率调整系统
公开(公告)号：US06789130B1
公开(公告)日：2004-09-07
申请号：US09571681
申请日：2000-05-16
申请人： Alain Benayoun , Jean-Francois Le Pennec , Michel Verhaeghe , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Michel Verhaeghe , Patrick Michel
IPC分类号： G06F1516
CPC分类号： H04L12/5602
摘要： Automatic speed adaptation system in a Local Area Network (LAN) between a hub (10) including a hub adapter (20, 24, 28) and at least a workstation (12, 14, 16) including a workstation adapter (18, 22, 26) for exchanging data over a link connected between the hub adapter and the workstation adapter at a rate based on a frequency which is inversely proportional to the length of the link. Each adapter comprises a clock generator for generating a clock having a frequency between F1 and F2 and processing means for transmitting at least a check frame from the hub adapter to the workstation adapter at a rate based on a frequency VCLK generated by the clock generator under the control of the processing means and selected as being the frequency corresponding to the length of the link, and for transmitting an acknowledge frame from the workstation adapter to the hub adapter thereby ascertaining that the selected frequency is the right frequency resulting in the best quality of transmission.
摘要翻译：在包括轮毂适配器（20,24,28）的轮毂（10）和至少包括工作站适配器（18,22）的工作站（12,14,16）之间的局域网（LAN）中的自动速度适配系统， 26），用于以基于与链路的长度成反比的频率的速率通过连接在中继适配器和工作站适配器之间的链路交换数据。每个适配器包括用于产生具有F1和F2之间的频率的时钟的时钟发生器和用于以基于由时钟发生器下的时钟发生器产生的频率VCLK的速率从集线器适配器至工作站适配器发送至少一个校验帧的处理装置处理装置的控制并被选择为对应于链路的长度的频率，并且用于将确认帧从工作站适配器发送到集线器适配器，从而确定所选择的频率是合适的频率，从而产生最佳传输质量。

15. 发明授权

US06516319B1 Parallelized processing device for processing search keys based upon tree structure 失效
标题翻译：基于树结构处理搜索键的并行处理设备
公开(公告)号：US06516319B1
公开(公告)日：2003-02-04
申请号：US09569493
申请日：2000-05-11
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , G06F17/3061 , G06F17/30952 , Y10S707/99933
摘要： A device for parallel processing of subtrees within a binary tree for searching for the tree leaf matching a search key. The search is performed at each node by applying a recursive function associated with each node and whose parameters depend on the node for determining which branch, left or right, is to be taken in accordance with the search key. The device includes subtree register blocks for storing the recursive functions, processors for processing the recursive functions, a control unit that assigns one processor to the processing of the recursive functions contained in a block that sent the request to the control unit, and means for selecting subtrees included in the sequence of branches between the root and the leaf defined in accordance with the search key in response to the processing of blocks.
摘要翻译：用于并行处理二进制树中的子树的装置，用于搜索与搜索关键字匹配的树叶。通过应用与每个节点相关联的递归函数并且其参数依赖于该节点来确定将根据搜索关键字被采取左侧或右侧的哪个分支来在每个节点处执行搜索。该装置包括用于存储递归函数的子树寄存器块，用于处理递归函数的处理器，将包含在向控制单元发送请求的块中的递归函数的处理分配给一个处理器的控制单元，以及用于选择子树包括在响应于块的处理的根据搜索关键字定义的根和叶之间的分支序列中。

16. 发明授权

US06510552B1 Apparatus for keeping several versions of a file 失效
标题翻译：用于保存文件的多个版本的设备
公开(公告)号：US06510552B1
公开(公告)日：2003-01-21
申请号：US09493193
申请日：2000-01-28
申请人： Alain Benayoun , Jacques Fieschi , Jean-François Le Pennec , Patrick Michel
发明人： Alain Benayoun , Jacques Fieschi , Jean-François Le Pennec , Patrick Michel
IPC分类号： G06F944
CPC分类号： G06F17/30067 , G06F8/71 , Y10S707/99953 , Y10S707/99954
摘要： An apparatus for keeping several versions of a file includes a memory and an overwriting unit coupled to the memory. An initial version of the file is stored in a first area of the memory, and a current version is stored in a second area of the memory, the current version resulting from a modification of the initial version. The overwriting unit substitutes the current version for the initial version in response to a validation signal. The validation signal is produced after the current version has been permanently stored.
摘要翻译：用于保存文件的多个版本的装置包括耦合到存储器的存储器和重写单元。文件的初始版本被存储在存储器的第一区域中，并且当前版本存储在存储器的第二区域中，当前版本是由初始版本的修改产生的。覆盖单元将当前版本替换为初始版本以响应验证信号。验证信号是在当前版本被永久存储之后产生的。

17. 发明授权

US06499061B1 Method and system for assigning labels to data flows over a packet switched network 有权
标题翻译：通过分组交换网络为数据流分配标签的方法和系统
公开(公告)号：US06499061B1
公开(公告)日：2002-12-24
申请号：US09330853
申请日：1999-06-11
申请人： Alain Benayoun , Jacques Fieschi , Claude Galand , Jean-François Le Pennec
发明人： Alain Benayoun , Jacques Fieschi , Claude Galand , Jean-François Le Pennec
IPC分类号： G06F1516
CPC分类号： H04L12/4641
摘要： Method and system for assigning labels in a data transmission network in which flows of data, composed of packets, are transmitted from a source node to a destination node through a plurality of switching nodes. The network is further characterized in that a label, identifying each flow of data, is added to each packet of the flow of data before the packet is transmitted from a transmitting node to an adjacent receiving node in the network. This so-called identification label is recognized by the receiving node as the identification of the flow of data to be transmitted. Each node in the network assigns an identification label to the packets when a new flow of data is received by the node. Both the transmitting and receiving nodes in the network generate an identical label for a given flow of data. Thus, the overhead associated with the sending of assigned labels from assigning nodes to corresponding upstream or downstream transmitting or receiving nodes in the network is avoided.
摘要翻译：在数据传输网络中分配标签的方法和系统，其中由分组组成的数据流通过多个交换节点从源节点传送到目的地节点。该网络的特征还在于，在将数据包从发送节点发送到网络中的相邻接收节点之前，将标识每个数据流的标签添加到数据流的每个分组。该所谓的识别标签被接收节点识别为要发送的数据流的标识。当节点接收到新的数据流时，网络中的每个节点都会为数据包分配一个标识标签。网络中的发送和接收节点都会为给定的数据流生成相同的标签。因此，避免了将分配的标签从分配节点发送到网络中的相应的上游或下游发送或接收节点所涉及的开销。

18. 发明授权

US06426953B1 Method of operating an internal high speed ATM bus inside a switching core 失效
标题翻译：在切换核心内部操作内部高速ATM总线的方法
公开(公告)号：US06426953B1
公开(公告)日：2002-07-30
申请号：US09189871
申请日：1998-11-10
申请人： Alain Benayoun , Patrick Michel , Claude Pin , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Claude Pin , Gilles Toubol
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/255 , H04L2012/5674
摘要： The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal of one bit of the data bus, S(0-31), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal. For the bus_ack cycle, an arbiter located in a control logic (102) determines which adapter has the bus granted for its data transfer by generating an acknowledge signal to the corresponding requester during one clock period following the deactivation of the synchronization signal. The next fourteen clock periods starts the xfer_cycle for transferring one ATM cell from a requester adapter to a destination adapter. At the end of this transmission, another req_cycle starts by the activation of the synchronization signal.
摘要翻译： ATM总线（100）由时钟信号CLK，同步信号-SYNC，数据总线S（0-31）和适配器识别总线SID（0-3）组成。它是以任何时钟速率运行的同步总线。时钟信号由背板（20）产生并发送到每个适配器（10-1，...，10-N）。在每个时钟周期期间，数据总线具有以下顺序定义的三个串行化操作模式（或周期）：1个时钟周期的bus_req周期，1个时钟周期的bus_ack周期和14个时钟周期的ATM cell_xfr周期。自由运行的同步信号在背板（20）上产生并被发送到每个适配器（10-1，...，10-N）。数据总线S（0-31）的一位的同步信号的激活开始bus_req循环。在每种情况下，剩余的数据总线信号保持在高阻抗状态。为了增加总线性能，同步信号保持有效，直到适配器激活其总线请求信号。对于bus_ack周期，位于控制逻辑（102）中的仲裁器通过在停止同步信号之后的一个时钟周期期间通过向对应的请求者生成确认信号来确定哪个适配器具有用于其数据传输的总线。接下来的十四个时钟周期启动xfer_cycle，用于将一个ATM信元从请求者适配器传输到目标适配器。在该传输结束时，通过同步信号的激活开始另一个req_cycle。

19. 发明授权

US06401188B1 Method for selection on a pattern sequence 有权
标题翻译：在图案序列上选择的方法
公开(公告)号：US06401188B1
公开(公告)日：2002-06-04
申请号：US09245189
申请日：1999-02-05
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F1202
CPC分类号： H04M15/8044 , H04M15/00 , H04M2215/42 , H04M2215/745
摘要： A method is disclosed for making a selection on a pattern sequence depending on whether or not the sequence belongs to a routing set, the routing set having at least two keys. The selection is made in a single step by analyzing a selection word (CASE SELECT) identifying the routing set.
摘要翻译：公开了一种用于根据序列是否属于路由集合对模式序列进行选择的方法，该路由集具有至少两个密钥。通过分析识别路由集的选择字（CASE SELECT），在单个步骤中进行选择。

20. 发明授权

US06331814B1 Adapter device for the transmission of digital data over an AC power line 失效
标题翻译：用于通过交流电源线传输数字数据的适配器设备
公开(公告)号：US06331814B1
公开(公告)日：2001-12-18
申请号：US09718186
申请日：2000-11-21
申请人： Andre Albano , Patrick Michel , Alain Benayoun , Jean-Francois Le Pennec
发明人： Andre Albano , Patrick Michel , Alain Benayoun , Jean-Francois Le Pennec
IPC分类号： H04M1104
CPC分类号： H04Q11/0471 , H04B3/54 , H04B2203/5408 , H04B2203/5454 , H04Q2213/1308 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13299 , H04Q2213/13302 , H04Q2213/1332
摘要： An adapter device for transmitting data from a local data-handling unit to a remote data-handling unit via an AC power line includes processing facilities that receive digital data from the local data-handling unit and transform the digital data into ISDN data. The adapter device also includes a burst transceiver circuit (BTC) that converts the ISDN data into low-voltage pseudo-ternary signals on a U interface. A transformer of the adapter device transforms the low-voltage pseudo-ternary signals into high-voltage pseudo-ternary signals and transmits the high-voltage pseudo-ternary signals via the AC power line. Such an adapter device may also be used for receiving the data from the local data-handling unit at the remote data-handling unit.
摘要翻译：用于经由AC电力线将数据从本地数据处理单元发送到远程数据处理单元的适配器装置包括从本地数据处理单元接收数字数据并将数字数据变换为ISDN数据的处理设备。适配器装置还包括将ISDN数据转换成U接口上的低电压伪三态信号的突发收发器电路（BTC）。适配器件的变压器将低电压伪三态信号转换为高电压伪三态信号，并通过AC电源线传输高电压伪三态信号。这样的适配器装置也可以用于从远程数据处理单元处的本地数据处理单元接收数据。

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