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11. 发明申请

US20060043369A1 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US20060043369A1
公开(公告)日：2006-03-02
申请号：US10927858
申请日：2004-08-27
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L29/76
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

12. 发明申请

US20050079723A1 METHOD FOR REMOVAL OF HYDROCARBON CONTAMINATION ON GATE OXIDE PRIOR TO NON-THERMAL NITRIDATION USING "SPIKE" RADICAL OXIDATION 有权
标题翻译：使用“SPIKE”辐射氧化除去非极性氮化物之前的氮氧化物上的碳氢化合物的方法
公开(公告)号：US20050079723A1
公开(公告)日：2005-04-14
申请号：US10684897
申请日：2003-10-14
申请人： Hiroaki Niimi , Husam Alshareef , Ajith Varghese
发明人： Hiroaki Niimi , Husam Alshareef , Ajith Varghese
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/306 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/36
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/28185 , H01L21/3144 , H01L21/31662
摘要： The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.
摘要翻译：本发明一般涉及一种在氮化步骤之前从基底去除烃类污染物的方法，其中提供基底的大致均匀的氮化。该方法包括将基板放置在处理室中并将氧源气体流入处理室。第一等离子体在处理室中形成第一预定量的时间，其中烃与一种或多种以自由基形式的氧源气体组合以形成产物气体。气体从处理室中移出，氮源气体流入处理室。然后在处理室中形成第二等离子体第二预定量的时间，其中以显着均匀的方式氮化基板。

13. 发明授权

US08828855B2 Transistor performance using a two-step damage anneal 有权
标题翻译：晶体管性能使用两步损伤退火
公开(公告)号：US08828855B2
公开(公告)日：2014-09-09
申请号：US11742229
申请日：2007-04-30
申请人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/425 , H01L21/265 , H01L21/8234 , H01L21/324 , H01L29/10
CPC分类号： H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
摘要翻译：两步热处理方法包括在半导体器件的硅衬底中进行离子注入。在半导体器件上执行第一热处理程序。在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

14. 发明申请

US20100032727A1 BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
标题翻译：混合定向技术（热）直接硅粘结（DSB）基板的边界区域缺陷减少
公开(公告)号：US20100032727A1
公开(公告)日：2010-02-11
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L27/092 , H01L21/20 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

15. 发明申请

US20080251864A1 STACKED POLY STRUCTURE TO REDUCE THE POLY PARTICLE COUNT IN ADVANCED CMOS TECHNOLOGY 审中-公开
标题翻译：堆叠聚合物结构降低高分子CMOS技术中的聚颗粒数
公开(公告)号：US20080251864A1
公开(公告)日：2008-10-16
申请号：US11733987
申请日：2007-04-11
申请人： Yuanning Chen , Stephanie W. Butler , Ajith Varghese , Narendra Singh Mehta
发明人： Yuanning Chen , Stephanie W. Butler , Ajith Varghese , Narendra Singh Mehta
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28044 , H01L29/6656 , H01L29/78 , Y02P80/30
摘要： A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions.
摘要翻译：一种用于实现堆叠栅极的方法，包括在半导体主体上形成栅极电介质，在栅极电介质上形成第一层栅电极材料，在栅电极材料的第一层上形成第二层栅电极材料，其中，栅极电极材料的第一层的晶粒尺寸分布不同于栅电极材料的第二层的晶粒尺寸分布，注入第一和第二栅极电极材料，图案化第一和第二栅极电极和栅极电介质，以及形成源区和漏区。

16. 发明授权

US07227201B2 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US07227201B2
公开(公告)日：2007-06-05
申请号：US10927858
申请日：2004-08-27
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L27/10
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

17. 发明申请

US20060046514A1 Thermal treatment of nitrided oxide to improve negative bias thermal instability 有权
标题翻译：氮化氧化物的热处理以改善负偏压热不稳定性
公开(公告)号：US20060046514A1
公开(公告)日：2006-03-02
申请号：US10930230
申请日：2004-08-31
申请人： Husam Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy Chancellor , Anand Krishnan , Malcolm Bevan
发明人： Husam Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy Chancellor , Anand Krishnan , Malcolm Bevan
IPC分类号： H01L21/31
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/02337 , H01L21/265 , H01L21/28202 , H01L21/3144 , H01L21/823857 , H01L29/518 , H01L29/7833
摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
摘要翻译：一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

18. 发明申请

US20080268627A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 有权
公开(公告)号：US20080268627A1
公开(公告)日：2008-10-30
申请号：US11742229
申请日：2007-04-30
申请人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/425
CPC分类号： H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

19. 发明申请

US20080268603A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 审中-公开
标题翻译：使用两步损伤天线的晶体管性能
公开(公告)号：US20080268603A1
公开(公告)日：2008-10-30
申请号：US11742186
申请日：2007-04-30
申请人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/324 , H01L27/1052
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
摘要翻译：两步热处理方法包括在半导体器件的硅衬底中进行离子注入。在半导体器件上执行第一热处理程序。在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

20. 发明申请

US20070054455A1 Method to obtain uniform nitrogen profile in gate dielectrics 有权
标题翻译：在栅极电介质中获得均匀氮分布的方法
公开(公告)号：US20070054455A1
公开(公告)日：2007-03-08
申请号：US11224219
申请日：2005-09-12
申请人： Ajith Varghese , Reima Laaksonen , Terrence Riley
发明人： Ajith Varghese , Reima Laaksonen , Terrence Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/823462 , H01L29/513 , H01L29/518 , Y10S438/981
摘要： The present invention provides, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.
摘要翻译：本发明在一个方面提供一种制造微电子器件100的方法，该方法包括在衬底115上沉积第一栅极电介质层160，使第一栅极电介质层160经受第一氮化处理，形成第二栅极电介质层165，并且具有小于第一栅极电介质层160的厚度的厚度，以及使第一和第二栅极电介质层160,165进行第二次氮化处理，其中第一和第二次氮化处理是不同的。本发明还提供了一种根据该方法制造的微电子器件100。

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