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181. 发明申请

US20060252043A1 Method for in vitro detection aberrant dysplasia, and the artificial nucleotides being used 审中-公开
标题翻译：用于体外检测异常发育不良的方法和使用的人造核苷酸
公开(公告)号：US20060252043A1
公开(公告)日：2006-11-09
申请号：US10549252
申请日：2003-03-13
申请人： Hua Bai , Yu Sun , Jing Zhou , Jiyou Li , Dajun Deng
发明人： Hua Bai , Yu Sun , Jing Zhou , Jiyou Li , Dajun Deng
IPC分类号： C12Q1/68 , C07H21/04
CPC分类号： C12Q1/6886 , C12Q2600/118 , C12Q2600/154
摘要： The present invention provides a method for in vitro detection of malignant potential of dysplasia by aberrant methylation of p16 CpG islands, comprising extraction of genomic DNA from a tissue or body fluid sample, analysis of methylation status of p16 CpG islands in the extracted DNA, and evaluation of malignant potential of the tested tissue. The present invention also provides DNA compositions having artificial sequences of p16 CpG islands with or without methylation.
摘要翻译：本发明提供了一种通过p16 CpG岛异常甲基化体外检测发育异常的恶性潜能的方法，包括从组织或体液样品中提取基因组DNA，分析提取的DNA中p16 CpG岛的甲基化状态，以及评估试验组织的恶性潜能。本发明还提供具有或不具有甲基化的p16 CpG岛的人工序列的DNA组合物。

182. 发明申请

US20060223278A1 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US20060223278A1
公开(公告)日：2006-10-05
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

183. 发明授权

US06995437B1 Semiconductor device with core and periphery regions 有权
标题翻译：具有核心和外围区域的半导体器件
公开(公告)号：US06995437B1
公开(公告)日：2006-02-07
申请号：US10869774
申请日：2004-06-16
申请人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
发明人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
IPC分类号： H01L31/119
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
摘要翻译：一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

184. 发明申请

US20050230714A1 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050230714A1
公开(公告)日：2005-10-20
申请号：US11066567
申请日：2005-02-28
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/80 , H01L31/112
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b）其浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区域（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

185. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

186. 发明授权

US06787840B1 Nitridated tunnel oxide barriers for flash memory technology circuitry 失效
标题翻译：用于闪存技术电路的氮化隧道氧化物屏障
公开(公告)号：US06787840B1
公开(公告)日：2004-09-07
申请号：US09492931
申请日：2000-01-27
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.
摘要翻译：具有多个闪存器件的半导体芯片，周边区域中的浅沟槽隔离以及芯区域中的LOCOS隔离。首先使用硬掩模来创建浅沟槽隔离。然后创建LOCOS隔离。随后的蚀刻用于去除桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化的隧道氧化物阻挡层。使用硬掩模来防止栅极氧化物层的氮化物污染。外围堆叠具有不同厚度的恶性氧化物层。

187. 发明授权

US06785080B1 Method and apparatus for providing a variable rate oversampling digital filter for resonance compensation in disk drive servo control systems 有权
标题翻译：用于在盘驱动器伺服控制系统中提供用于共振补偿的可变速率过采样数字滤波器的方法和装置
公开(公告)号：US06785080B1
公开(公告)日：2004-08-31
申请号：US09974454
申请日：2001-10-09
申请人： Yu Sun , Don Brunnett , XiaoPing Hu
发明人： Yu Sun , Don Brunnett , XiaoPing Hu
IPC分类号： G11B2102
CPC分类号： G11B5/59622
摘要： A method and apparatus for controlling the position of a disk drive transducer head relative to a target track are provided. An oversampled control output allows frequencies that are higher than the Nyquist frequency of the servo control system to be filtered. The system initiates a plurality of control outputs during a single sampling period, allowing the use of a single processor interrupt for each sampling period. The outputs initiated during a single sampling period may be of unequal length. In addition, the outputs may be proportioned so that the total control energy provided to the actuator is equal to the control energy that would be provided by control outputs initiated every one-half sampling period.
摘要翻译：提供了一种用于控制盘驱动器换能器头相对于目标轨道的位置的方法和装置。过采样控制输出允许高于伺服控制系统的奈奎斯特频率的频率进行滤波。系统在单个采样周期内启动多个控制输出，允许在每个采样周期使用单个处理器中断。在单个采样周期期间发起的输出可能具有不相等的长度。此外，输出可以成比例，使得提供给致动器的总控制能量等于由每半个采样周期启动的控制输出将提供的控制能量。

188. 发明授权

US06737703B1 Memory array with buried bit lines 失效
标题翻译：内存阵列带埋线
公开(公告)号：US06737703B1
公开(公告)日：2004-05-18
申请号：US10095512
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad , Yu Sun
发明人： Richard Fastow , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.
摘要翻译：在存储器件中，衬底在衬底中具有多个源极/漏极区域。在源极/漏极区之间是填充有氧化物的沟槽。导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

189. 发明授权

US06605511B2 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation 失效
标题翻译：形成用于闪存技术电路的氮化隧道氧化物屏障的方法和STI和LOCOS隔离
公开(公告)号：US06605511B2
公开(公告)日：2003-08-12
申请号：US10295738
申请日：2002-11-15
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L218234
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/1052 , Y10S438/981
摘要： A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
摘要翻译：提供了一种通过首先使用硬掩模创建浅沟槽隔离来制造在外围区域中具有浅沟槽隔离和芯区域中的LOCOS隔离的改进的闪速存储器件的方法; 然后创建LOCOS隔离; 并随后蚀刻以除去桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化隧道氧化物层。使用硬掩模来防止栅极氧化物层的氮化物污染。

190. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

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