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161. 发明授权

US07692944B2 3-dimensional integrated circuit architecture, structure and method for fabrication thereof 有权
标题翻译：三维集成电路体系结构及其制造方法
公开(公告)号：US07692944B2
公开(公告)日：2010-04-06
申请号：US12127086
申请日：2008-05-27
申请人： Kerry Bernstein , Paul W. Coteus , Philip G. Emma
发明人： Kerry Bernstein , Paul W. Coteus , Philip G. Emma
IPC分类号： G11C5/02
CPC分类号： H01L27/0688 , H01L21/6835 , H01L21/8221 , H01L27/105 , H01L27/1052 , H01L2221/68359 , H01L2225/06541 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
摘要翻译：其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。所有层可以独立供电以提供额外的性能增强。

162. 发明授权

US07685392B2 Providing indeterminate read data latency in a memory system 失效
标题翻译：在存储器系统中提供不确定的读取数据延迟
公开(公告)号：US07685392B2
公开(公告)日：2010-03-23
申请号：US11289193
申请日：2005-11-28
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/372 , G06F13/376
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received and storing it into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle, and in response thereto the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. The upstream data packet is selectively transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.
摘要翻译：一种用于在存储器系统中提供不确定的读取数据延迟的方法。该方法包括确定本地数据分组是否已被接收并将其存储到缓冲设备中。该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上游驱动器是空闲的，并且响应于此数据包被发送到上游驱动器。该方法还包括确定是否已经接收到上游数据分组，并且上游驱动器不空闲，则上游数据分组被存储到缓冲设备中。上游数据包被选择性地发送到上游驱动器。如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

163. 发明授权

US07650434B2 Global tree network for computing structures enabling global processing operations 失效
标题翻译：用于计算结构的全局树网络，实现全球处理操作
公开(公告)号：US07650434B2
公开(公告)日：2010-01-19
申请号：US10469000
申请日：2002-02-25
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/17337
摘要： A system and method for enabling high-speed, low-latency global tree network communications among processing nodes interconnected according to a tree network structure. The global tree network enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the tree via links to facilitate performance of low-latency global processing operations at nodes of the virtual tree and sub-tree structures. The global operations performed include one or more of: broadcast operations downstream from a root node to leaf nodes of a virtual tree, reduction operations upstream from leaf nodes to the root node in the virtual tree, and point-to-point message passing from any node to the root node. The global tree network is configurable to provide global barrier and interrupt functionality in asynchronous or synchronized manner, and, is physically and logically partitionable.
摘要翻译：一种用于根据树网络结构互连的处理节点之间实现高速，低延迟的全局树网络通信的系统和方法。全局树网络使得能够在具有多个互连的处理节点的计算机结构中执行并行算法操作期间执行集合缩减操作。包括通过链路互连树节点的路由器设备，以便于在虚拟树和子树结构的节点处执行低延迟全局处理操作。执行的全局操作包括以下一个或多个：从根节点向下游到虚拟树的叶节点的广播操作，从叶节点向上到叶节点到虚拟树中的根节点的减少操作，以及从任何节点到根节点。全局树网络可配置为以异步或同步方式提供全局屏障和中断功能，并且在物理和逻辑上可分区。

164. 发明申请

US20100000085A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
标题翻译：土地网阵列（LGA）利用金属激光器热电偶和其他多点接触几何
公开(公告)号：US20100000085A1
公开(公告)日：2010-01-07
申请号：US12047694
申请日：2008-03-13
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H05K3/10
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造模块装置的方法，其包括包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机

165. 发明授权

US07641479B2 Land grid array interposer (LGA) utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries that is constituted of a moldable dielectric elastometric material 失效
标题翻译：利用金属弹性体半环和其他多点接触几何构成的Land Grid阵列插入器（LGA），其由可模制的介电弹性材料构成
公开(公告)号：US07641479B2
公开(公告)日：2010-01-05
申请号：US12047664
申请日：2008-03-13
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机

166. 发明申请

US20090320282A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
公开(公告)号：US20090320282A1
公开(公告)日：2009-12-31
申请号：US12106462
申请日：2008-04-21
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R43/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

167. 发明授权

US07627732B2 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US07627732B2
公开(公告)日：2009-12-01
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/50 , H04Q11/00
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

168. 发明授权

US07613368B2 Mixed electrical and optical LGA interposer for facilitating chip to board communications by dual signal types 有权
标题翻译：混合电和光LGA插入器，用于通过双信号类型促进芯片到板通信
公开(公告)号：US07613368B2
公开(公告)日：2009-11-03
申请号：US10988220
申请日：2004-11-12
申请人： Gareth G. Hougham , Russell A. Budd , Punit P. Chiniwalla , Paul W. Coteus , Alphonso P. Lanzetta , Frank R. Libsch
发明人： Gareth G. Hougham , Russell A. Budd , Punit P. Chiniwalla , Paul W. Coteus , Alphonso P. Lanzetta , Frank R. Libsch
IPC分类号： G02B6/12
CPC分类号： G02B6/43
摘要： Integrated optoelectronic chips or collections of chips on a module that have both electrical as well as optical interconnects offer many advantages in speed, power consumption and heat generation. Mixed signal types, however, pose significant packaging challenges. This invention describes a land grid array (LGA) interposer which can simultaneously connect electrical and optical signals from a module to a printed circuit board.
摘要翻译：集成的光电芯片或芯片集合在具有电和光互连的模块上，在速度，功耗和发热方面提供许多优点。然而，混合信号类型构成重大的封装挑战。本发明描述了一种能够将来自模块的电和光信号同时连接到印刷电路板的平面栅格阵列（LGA）插入器。

169. 发明授权

US07587516B2 Class network routing 失效
标题翻译：类网络路由
公开(公告)号：US07587516B2
公开(公告)日：2009-09-08
申请号：US10468999
申请日：2002-02-25
申请人： Gyan Bhanot , Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Gyan Bhanot , Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/173 , H04L12/66 , H04L12/50
CPC分类号： H04L45/16 , H04L45/06
摘要： Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.
摘要翻译：在诸如包括在其节点处的多个并行计算处理器的计算机网络的网络中实现类网络路由。类网络路由允许计算处理器将消息广播到计算机网络中的其他计算处理器的范围（一个或多个），例如列或行中的处理器。通常这种类型的操作需要单独的消息发送到每个处理器。根据本发明的类网络路由，单个消息是足够的，这通常减少了网络中的消息总数以及进行广播的延迟。类网络路由也适用于具有硬件类功能（组播）能力的分布式存储并行超级计算机上的密集矩阵求逆算法。这是通过利用密集矩阵反演的通信模式可以通过硬件类功能来实现的，这导致更快的执行时间。

170. 发明申请

US20090113133A1 Synchronous Memory Having Shared CRC and Strobe Pin 失效
标题翻译：具有共享CRC和选通引脚的同步存储器
公开(公告)号：US20090113133A1
公开(公告)日：2009-04-30
申请号：US11923691
申请日：2007-10-25
申请人： Kyu-Hyoun Kim , Paul W. Coteus
发明人： Kyu-Hyoun Kim , Paul W. Coteus
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F11/1004
摘要： A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.
摘要翻译：具有存储元件芯片（DRAM）的存储器系统和具有用于传送数据的多个驱动器和接收器以及锁存器的存储器控制器芯片。对于写时钟，写入数据和写入CRC（循环冗余校验）从存储器控制器传送到DRAM，并锁存进行错误检查。读取被计时，并且读取的数据被接收并被传送到读取数据锁存器，同时还接收用于从DRAM确认数据完整性的时钟读选通脉冲。每个芯片都有一个双功能引脚，在写入期间充当共享的CRC引脚，并在读取期间充当共享的选通引脚。具有CRC信号和DQS信号的数据传输通过两个路径CRC0 / DQS和CRC1 / DQS1传送。也可以通过CRC0 / DQS信号在一个路径上传送CRC信号。读操作没有CRC，并且不需要CRC，因为可以通过存储器纠错编码（ECC）来检测读取期间的传输错误。写入数据将源同步I / O数据提供给调制解调器高速存储器通信所需的所述存储器元件芯片。

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