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161. 发明授权

US07049702B2 Damascene structure at semiconductor substrate level 有权
标题翻译：半导体衬底级别的镶嵌结构
公开(公告)号：US07049702B2
公开(公告)日：2006-05-23
申请号：US10640757
申请日：2003-08-14
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L29/40
CPC分类号： H01L21/76846 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.
摘要翻译：半导体衬底级别的镶嵌结构和工艺。在半导体衬底上设置预金属电介质层，该开口露出衬底上的接触区域。在暴露的接触区域上设置有缓冲金属层，在开口的内部设有阻挡层。导体设置在缓冲金属层上，基本上填充开口以电连接到接触区域。

162. 发明申请

US20060055065A1 HV-MOS and mixed-signal circuit structure with low-k interconnection 审中-公开
标题翻译： HV-MOS和低k互连的混合信号电路结构
公开(公告)号：US20060055065A1
公开(公告)日：2006-03-16
申请号：US10938480
申请日：2004-09-10
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Syun-Ming Jang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L31/109
CPC分类号： H01L27/12 , G02F1/13452 , H01L27/0629 , H01L27/105 , H01L27/1052
摘要： A semiconductor chip comprises a fast device formed on a semiconductor substrate and a high-voltage metal-oxide-semiconductor transistor (HV-MOS) formed on the semiconductor substrate and an interconnect isolation feature having a low-k dielectric material disposed over the fast device and the HV-MOS in the semiconductor substrate.
摘要翻译：半导体芯片包括形成在半导体衬底上的快速器件和形成在半导体衬底上的高压金属氧化物半导体晶体管（HV-MOS），以及布置在快速器件上的具有低k电介质材料的互连隔离特征和半导体衬底中的HV-MOS。

163. 发明申请

US20060033136A1 MRAM over sloped pillar 有权
标题翻译： MRAM倾斜柱
公开(公告)号：US20060033136A1
公开(公告)日：2006-02-16
申请号：US10917585
申请日：2004-08-13
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
IPC分类号： G11C11/15 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L43/08 , B82Y10/00 , G11C11/15 , H01L27/228
摘要： An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.
摘要翻译：一种装置，包括位于衬底上方的柱，并且具有相对于衬底以锐角定向的至少一个倾斜表面。该装置还包括基本上符合倾斜表面的MRAM堆叠，因此MRAM堆叠也相对于衬底以锐角取向。 MRAM堆叠可以包括多个基本上平面的平行层，每个平行层相对于衬底以锐角取向。

164. 发明授权

US06977218B2 Method for fabricating copper interconnects 失效
公开(公告)号：US06977218B2
公开(公告)日：2005-12-20
申请号：US10621676
申请日：2003-07-17
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76867
摘要： A method for capping copper or copper alloy interconnects. A dielectric layer is formed overlaying a semiconductor substrate. An opening is formed in the dielectric layer and subsequently embedded copper or copper alloy form an interconnect structure. A silicon layer is formed on the copper or copper alloy by sputtering or chemical vapor deposition. A copper silicide layer is formed by reacting the silicon layer with the underlying copper or copper alloy as a capping layer.

165. 发明申请

US20050236616A1 Reliable semiconductor structure and method for fabricating 审中-公开
标题翻译：可靠的半导体结构和制造方法
公开(公告)号：US20050236616A1
公开(公告)日：2005-10-27
申请号：US10831981
申请日：2004-04-26
申请人： Horng-Huei Tseng , Chung-Hu Ge , Chao-Hsiung Wang
发明人： Horng-Huei Tseng , Chung-Hu Ge , Chao-Hsiung Wang
IPC分类号： H01L21/00 , H01L21/66 , H01L23/544 , H01L29/02 , H01L29/04
CPC分类号： H01L23/544 , H01L21/67115 , H01L29/045 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.
摘要翻译：可靠的半导体结构及其制造方法。半导体衬底上的有源区和/或划线沿着耐裂纹结晶方向配置。可以避免由于快速热处理的突然温度斜坡导致的热裂纹。

166. 发明申请

US20050231695A1 Method and system for immersion lithography using high PH immersion fluid 审中-公开
标题翻译：使用高PH浸液的浸没式光刻方法和系统
公开(公告)号：US20050231695A1
公开(公告)日：2005-10-20
申请号：US10824750
申请日：2004-04-15
申请人： Chao -Hsiung Wang , Horng-Huei Tseng
发明人： Chao -Hsiung Wang , Horng-Huei Tseng
IPC分类号： G03B27/42 , G03F7/00 , G03F7/20 , H01L21/027
CPC分类号： G03F7/70341
摘要： A method and system is disclosed for conducting immersion photolithography. The system includes at least one lens for transmitting a predetermined radiation on a predetermined product substrate, and a fluid volume in contact with the lens on its first end and with the product substrate on its second end, wherein the fluid volume has a molar concentration of hydroxyl ions more than 10−7 mole per liter.
摘要翻译：公开了用于进行浸没光刻的方法和系统。该系统包括用于在预定产品基底上传送预定辐射的至少一个透镜，以及与其第一端上的透镜接触的流体体积和其第二端上的产品基底，其中流体体积的摩尔浓度为羟基离子大于10 -7摩尔/升。

167. 发明申请

US20050224986A1 Stable metal structure with tungsten plug 有权
标题翻译：稳定的金属结构与钨丝塞
公开(公告)号：US20050224986A1
公开(公告)日：2005-10-13
申请号：US10919875
申请日：2004-08-17
申请人： Horng-Huei Tseng , Syun-Ming Jang
发明人： Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/768 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76835 , H01L21/76852 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In the preferred embodiment, a thick regular-k dielectric is formed on a substrate. A tungsten plug is formed in the thick regular-k dielectric. The thick regular-k dielectric is recessed and a thin low-k dielectric is formed on the thick regular-k dielectric. The thin low-k dielectric acts as a glue layer and as an etch stop layer. A thick low-k dielectric is formed on the thin low-k material. Optionally, an opening is formed through the thick low-k dielectric to expose the tungsten plug. The opening is then filled with copper or copper alloys.
摘要翻译：在优选实施例中，在基板上形成厚的正常k电介质。在厚规则k电介质中形成钨塞。厚的普通k电介质是凹陷的，并且在厚的规则k电介质上形成薄的低k电介质。薄的低k电介质用作胶层和作为蚀刻停止层。在薄的低k材料上形成厚的低k电介质。可选地，通过厚的低k电介质形成开口以暴露钨插塞。然后用铜或铜合金填充开口。

168. 发明申请

US20050189598A1 Logic embedded-memory integrated circuits 审中-公开
标题翻译：逻辑嵌入式存储器集成电路
公开(公告)号：US20050189598A1
公开(公告)日：2005-09-01
申请号：US10826899
申请日：2004-04-16
申请人： Syun-Ming Jang , Horng-Huei Tseng
发明人： Syun-Ming Jang , Horng-Huei Tseng
IPC分类号： H01L21/314 , H01L21/336 , H01L21/8239 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/11 , H01L27/115 , H01L29/51
CPC分类号： H01L29/518 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115 , H01L27/11502 , H01L27/11531 , H01L27/1159
摘要： A semiconductor device and a method for fabricating such a device is disclosed. In one example, the semiconductor device includes a substrate, one or more logic devices formed over the substrate, and one or more memory devices formed over the substrate. The logic device may include a high dielectric constant (high-k) gate dielectric, while the memory device may include a non-high-k gate dielectric.
摘要翻译：公开了半导体器件及其制造方法。在一个示例中，半导体器件包括衬底，在衬底上形成的一个或多个逻辑器件以及形成在衬底上的一个或多个存储器件。逻辑器件可以包括高介电常数（high-k）栅极电介质，而存储器件可以包括非高k栅极电介质。

169. 发明申请

US20050054191A1 Interconnect with composite barrier layers and method for fabricating the same 有权
公开(公告)号：US20050054191A1
公开(公告)日：2005-03-10
申请号：US10654757
申请日：2003-09-04
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

170. 发明授权

US06847098B1 Non-floating body device with enhanced performance 有权
标题翻译：非浮体装置具有增强的性能
公开(公告)号：US06847098B1
公开(公告)日：2005-01-25
申请号：US10641575
申请日：2003-08-14
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L23/58 , H01L24/06
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer. Subsequent silicon oxide deposition and planarization procedures results in a first portion of the strained silicon layer overlying the silicon alloy layer while a second portion overlays a buried oxide region. A semiconductor device is then formed in the strained silicon layer, with specific elements of the semiconductor device located on a buried oxide region.
摘要翻译：已经开发了在半导体衬底中形成掩埋氧化硅区域的方法，其中形成在应变硅形状的部分下方的掩埋氧化硅区域的部分以及应变硅形状用于容纳半导体器件的方法。本发明的第一实施例的特征在于通过热氧化工艺在硅合金层中形成的掩埋氧化物区域。在热氧化过程中保护的应变硅层的第一部分覆盖硅合金层，而应变硅层的第二部分覆盖掩埋氧化物区域。本发明的第二实施例的特征在于用于在硅合金层中形成各向同性开口的各向同性干法蚀刻程序，其中开口横向延伸在应变硅层的一部分下方。随后的氧化硅沉积和平坦化过程导致覆盖硅合金层的应变硅层的第一部分，而第二部分覆盖掩埋氧化物区域。然后在应变硅层中形成半导体器件，其中半导体器件的特定元件位于掩埋氧化物区域上。

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