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    • 159. 发明申请
    • ENHANCING PERFORMANCE OF A MEMORY UNIT OF A DATA PROCESSING DEVICE BY SEPARATING READING AND FETCHING FUNCTIONALITIES
    • 通过分离读取和切断功能来提高数据处理设备的存储单元的性能
    • WO2006087665A3
    • 2007-01-18
    • PCT/IB2006050461
    • 2006-02-13
    • KONINKL PHILIPS ELECTRONICS NVPETERS HARM J A MSETHURAMAN RAMANATHANVELDMAN GERARDMEUWISSEN PATRICK P E
    • PETERS HARM J A MSETHURAMAN RAMANATHANVELDMAN GERARDMEUWISSEN PATRICK P E
    • G06F12/08
    • H04N19/433G06F12/0862G06F12/0875G06F12/0897G06T7/20G06T2200/28G09G5/395G09G2320/0261G09G2360/121H04N19/436
    • The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.
    • 本发明涉及包括处理单元(12)和存储单元(14)的数据处理设备(10),以及用于控制数据处理设备的存储单元(14)的操作的方法。 存储器单元(14)包括主存储器(16),低级高速缓存存储器(20.2),其直接连接到处理单元(12)并且适于保持当前活动的滑动搜索区域的所有像素用于读取 处理单元(12)的访问,连接在低级缓存存储器和帧存储器之间的高级缓存存储器(18)和第一预取缓冲器(20.1) 高级缓存存储器和低级高速缓存存储器,并且其适于保持像素块的一个搜索区域列或一个搜索区域行,这取决于处理单元后面的扫描方向和扫描顺序。 读取和取出功能在存储器单元(14)中解耦。 获取功能集中在较高的缓存级别,而读取功能集中在较低的缓存级别。 这样可以实现并行读取和取出,从而提高数据处理设备的性能。