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151. 发明申请

US20100038705A1 FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION 审中-公开
标题翻译：具有门极电极边缘的场效应器件增强型电介质和制造方法
公开(公告)号：US20100038705A1
公开(公告)日：2010-02-18
申请号：US12190109
申请日：2008-08-12
申请人： Bruce B. Doris , Kangguo Cheng , Haining S. Yang
发明人： Bruce B. Doris , Kangguo Cheng , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/28026 , H01L21/28194 , H01L29/512 , H01L29/66553 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.
摘要翻译：半导体结构和用于制造半导体结构的方法在诸如场效应晶体管结构的场效应结构内的与栅电极相邻的间隔物之下提供底切。可以完全或不完全地覆盖插入在间隔物和半导体衬底之间的区域的底切部被栅极电介质填充。与栅极和半导体衬底相比，栅极电介质具有比间隔物和半导体衬底之间更大的厚度。可以使用顺序替换栅极电介质和栅极电极法制造半导体结构。

152. 发明申请

US20090298244A1 Mobility Enhanced FET Devices 审中-公开
标题翻译：移动增强型FET器件
公开(公告)号：US20090298244A1
公开(公告)日：2009-12-03
申请号：US12537275
申请日：2009-08-07
申请人： Bruce B. Doris , Cyril Cabral, JR. , Elizabeth A. Duch , Stephen M. Rossnagel , Michelle L. Steen
发明人： Bruce B. Doris , Cyril Cabral, JR. , Elizabeth A. Duch , Stephen M. Rossnagel , Michelle L. Steen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4958 , H01L29/7845
摘要： NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.
摘要翻译：具有单独应力通道区域的NFET和PFET器件及其制造方法。公开了一种FET，其包括栅极，该栅极包括处于第一应力状态的金属。 FET还包括托管在单晶Si基材料中的沟道区域，该沟道区域被栅极覆盖并处于第二应力状态。沟道区域的第二应力状态与包括在栅极中的金属的第一应力状态相反。 NFET通道通常处于应力的拉伸状态，而PFET通道通常处于应力的压缩状态。制造方法包括通过物理气相沉积（PVD）沉积金属层，使得层处于应力状态。

153. 发明申请

US20090203200A1 GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH 失效
标题翻译：具有自对准独立门控阀的门控方案
公开(公告)号：US20090203200A1
公开(公告)日：2009-08-13
申请号：US12027444
申请日：2008-02-07
申请人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
发明人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/266 , H01L21/28123 , H01L21/823828
摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
摘要翻译：公开了一种用于自对准栅极图案化的方法。使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。选择掩模材料以便于选择性蚀刻。当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

154. 发明申请

US20090179283A1 METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的金属栅极堆叠和半导体栅极堆叠
公开(公告)号：US20090179283A1
公开(公告)日：2009-07-16
申请号：US11954918
申请日：2007-12-12
申请人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
发明人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
摘要翻译：包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

155. 发明申请

US20090149010A1 STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
标题翻译：用于制造SiGe和/或Si：C的栅极应力工程的散装硅和SOI MOS器件中的分离自由应力通道的结构和方法
公开(公告)号：US20090149010A1
公开(公告)日：2009-06-11
申请号：US12352504
申请日：2009-01-12
申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen
发明人： Huilong Zhu , Bruce B. Doris , Huajie Chen
IPC分类号： H01L21/18
CPC分类号： H01L29/7845 , H01L21/28035 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/4925 , H01L29/66545 , H01L29/7842
摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.
摘要翻译：公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

156. 发明申请

US20090140347A1 METHOD AND STRUCTURE FOR FORMING MULTIPLE SELF-ALIGNED GATE STACKS FOR LOGIC DEVICES 有权
标题翻译：形成用于逻辑设备的多个自对准栅格堆叠的方法和结构
公开(公告)号：US20090140347A1
公开(公告)日：2009-06-04
申请号：US11950095
申请日：2007-12-04
申请人： Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
发明人： Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823842
摘要： A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.
摘要翻译：一种用于形成多个自对准栅极堆叠的方法，所述方法包括：在衬底的第一部分上形成第一组栅极堆叠层，在所述衬底的邻近所述第一部分的第二部分上形成第二组栅极堆叠层蚀刻以形成设置在衬底的第一部分和第二部分之间的沟槽，并用绝缘材料填充沟槽。

157. 发明授权

US07488658B2 Stressed semiconductor device structures having granular semiconductor material 有权
标题翻译：具有粒状半导体材料的强调半导体器件结构
公开(公告)号：US07488658B2
公开(公告)日：2009-02-10
申请号：US11531372
申请日：2006-09-13
申请人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

158. 发明授权

US07476580B2 Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C 有权
标题翻译：通过SiGe和/或Si：C的栅极应力工程制造体硅和SOI CMOS器件中无位错应力通道的结构和方法
公开(公告)号：US07476580B2
公开(公告)日：2009-01-13
申请号：US11931387
申请日：2007-10-31
申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen
发明人： Huilong Zhu , Bruce B. Doris , Huajie Chen
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7845 , H01L21/28035 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/4925 , H01L29/66545 , H01L29/7842
摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.
摘要翻译：公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

159. 发明授权

US07476579B2 Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film 有权
标题翻译：用强调膜增强nMOSFET和pMOSFET性能的方法和结构
公开(公告)号：US07476579B2
公开(公告)日：2009-01-13
申请号：US11560925
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L21/336
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

160. 发明申请

US20090011552A1 METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
标题翻译：金属门CMOS至少具有单栅极金属和双栅电极
公开(公告)号：US20090011552A1
公开(公告)日：2009-01-08
申请号：US12210703
申请日：2008-09-15
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少单个栅极金属，并且nFET栅极堆叠被设计为具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

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