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141. 发明专利

JP2005020083A Clock generating circuit 有权
标题翻译：时钟发生电路
公开(公告)号：JP2005020083A
公开(公告)日：2005-01-20
申请号：JP2003178416
申请日：2003-06-23
申请人： Renesas Lsi Design Corp , Renesas Technology Corp , 株式会社ルネサスLsiデザイン , 株式会社ルネサステクノロジ
发明人： ARAKI MASAHIRO , HAYASHI CHIEKO
IPC分类号： G06F1/04 , H03K3/03 , H03K5/00 , H03K5/13 , H03L7/081 , H03L7/099 , H03L7/18 , H03L7/23 , H04L7/02
CPC分类号： H03L7/0812 , H03L7/081 , H03L7/0996 , H03L7/23 , H03L7/235
摘要： PROBLEM TO BE SOLVED: To provide a spread spectrum clock generating circuit capable of conducting frequency modulation with high accuracy. SOLUTION: In the spread spectrum clock generating circuit, a DLL circuit 8 delays the oscillation clock signal CLKO from a VCO 7 and outputs delayed clock signals CLKD1 to CLKD10 having different phases respectively. A selector 9 selects one of the delayed clock signals CLKD1 to CLKD10, and outputs a selected clock signal CLKS. A control circuit 3 controls a signal selection operation of the selector 9. A feedback frequency divider 10 divides a frequency of the selected clock signal CLKS by a frequency division ratio N, and generates a comparison clock signal CLKC. In this manner, a phase of the comparison clock signal CLKC can be fine-tuned. Therefore, the spread spectrum clock generating circuit capable of conducting frequency modulation with high accuracy can be obtained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够以高精度进行频率调制的扩频时钟发生电路。解扩：在扩频时钟发生电路中，DLL电路8将来自VCO7的振荡时钟信号CLKO延迟，分别输出具有不同相位的延迟时钟信号CLKD1〜CLKD10。选择器9选择延迟时钟信号CLKD1至CLKD10中的一个，并输出所选择的时钟信号CLKS。控制电路3控制选择器9的信号选择操作。反馈分频器10将选择的时钟信号CLKS的频率除以分频比N，并产生比较时钟信号CLKC。以这种方式，可以微调比较时钟信号CLKC的相位。因此，可以获得能够高精度地进行频率调制的扩频时钟发生电路。版权所有（C）2005，JPO＆NCIPI

142. 发明专利

JP2004508747A Method and device for locking vertically input video signal and the output video signal 有权
公开(公告)号：JP2004508747A
公开(公告)日：2004-03-18
申请号：JP2002524133
申请日：2000-12-29
申请人：アールジイビイ・システムズ・インコーポレーテッド
发明人：タラチ，ブライアン・リチャード , ツロン，ドゥイ・ドゥー
IPC分类号： H04N5/04 , G09G5/00 , G09G5/18 , G09G5/391 , H03L7/23 , H04N5/06 , H04N5/12 , H04N5/268 , H04N5/44 , H04N5/46 , H04N5/74 , H04N7/10 , H04N9/64
CPC分类号： G09G5/006 , H03L7/235 , H04N5/126 , H04N5/268 , H04N5/4401 , H04N5/46 , H04N5/74 , H04N7/012 , H04N7/104 , H04N9/641 , H04N9/642 , H04N21/4113
摘要：本発明は、入力と出力のビデオ・フレーム・レートを垂直にロックさせるための方法および装置を記述する。入力フォーマットおよび周波数にかかわらず、出力垂直同期パルスが入力垂直同期パルスと同相でロックされる。出力解像度、水平リフレッシュ・レート、および遅延は、すべてユーザによって選択可能である。２つの位相ロック・ループを直列に接続して、入力フレームと出力フレームの間の垂直ロックを達成する。入力フレームと出力フレームの間で垂直同期パルスをロックすることにより、異なる入力フレームからのピクセルが１つの出力フレーム中で混合することがなくなる。第１の位相ロック・ループは、ユーザの表示選好を満たすのに必要な出力ピクセル・クロックを生成するが、現在の位相ロック・ループは整数分周器を使用するので、フレームのロックに必要な所望の出力ピクセル・クロックを正確に表さない場合がある。第２の位相ロック・ループが、第１の位相ロック・ループへの基準周波数であるその出力を、ロックが達成されるまで調節する。

143. 发明专利

JP2004072714A Clock generating system 审中-公开
公开(公告)号：JP2004072714A
公开(公告)日：2004-03-04
申请号：JP2003115774
申请日：2003-04-21
申请人： Rohm Co Ltd , ローム株式会社
发明人： ONISHI MASAKI , FUJIWARA MASAO
IPC分类号： G06F1/06 , G11B20/14 , H03L7/087 , H03L7/22 , H03L7/23
CPC分类号： H03L7/23 , G06F1/06 , G11B20/1403
摘要： PROBLEM TO BE SOLVED: To acquire an efficient S/N (signal to noise ratio) in first to third reference frequency clocks each having predetermined ratio in relation to a certain reference clock by using a PLL circuit in spite of limitations in the S/N of noise floor. SOLUTION: The first reference frequency clock is inputted to a first PLL circuit as the reference clock, and an intermediate frequency clock having a first predetermined ratio in relation to the reference clock is generated. The intermediate frequency clock is inputted to a second PLL circuit and a third PLL circuit. The second reference frequency clock having a second predetermined ratio in relation to the reference clock is generated, and the third reference frequency clock having a third predetermined ratio in relation to the reference clock is generated. COPYRIGHT: (C)2004,JPO

144. 发明专利

JP2004056409A Phase locked loop circuit employing fractional frequency divider 审中-公开
$Phase locked loop circuit employing fractional frequency divider$
公开(公告)号：JP2004056409A
公开(公告)日：2004-02-19
申请号：JP2002210396
申请日：2002-07-19
申请人： Ando Electric Co Ltd , 安藤電気株式会社
发明人： MAEDA MINORU
IPC分类号： H03L7/22 , H03L7/18 , H03L7/197 , H03L7/23
CPC分类号： H03L7/1806 , H03L7/1974 , H03L7/23
摘要： PROBLEM TO BE SOLVED: To provide a phase locked loop circuit capable of obtaining an output frequency not causing a fractional figure even when a reference signal has a round frequency (e.g. 10MHz). SOLUTION: The phase locked loop circuit includes: a first PLL stage wherein a signal resulting from frequency-dividing an output of a first voltage-controlled oscillator by a first fractional frequency divider is compared with a reference frequency and a resulting deviation is given to the first voltage-controlled oscillator via a low pass filter to control an output frequency of the first voltage-controlled oscillator; and a second fractional frequency divider that frequency-divides the output of the first PLL stage and gives the result to a second PLL stage as its reference signal frequency signal, and an output signal from a second voltage-controlled oscillator of the second PLL stage is extracted. COPYRIGHT: (C)2004,JPO

145. 发明专利

JP2003511948A 失效
公开(公告)号：JP2003511948A
公开(公告)日：2003-03-25
申请号：JP2001530207
申请日：2000-09-28
IPC分类号： G01R31/316 , G01R31/28 , G01R31/3183 , H03K5/00 , H03K5/156 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/22 , H03L7/23

146. 发明专利

JP2002100985A HIGH-RESOLUTION FREQUENCY ADJUSTMENT METHOD AND DEVICE FOR MULTI-STAGE FREQUENCY SYNTHESIZER 审中-公开
公开(公告)号：JP2002100985A
公开(公告)日：2002-04-05
申请号：JP2001221160
申请日：2001-07-23
申请人： IBM
发明人： DAVID WILLIAM BOOSURAA , MARK EDWARD DEAN , NGO HUNG CAI , ANDREW CHRISTIAN ZIMMERMAN
IPC分类号： H03L7/22 , H03L7/08 , H03L7/23 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for adjusting the generated frequency, especially a frequency synthesizer capable of performing the frequency adjustment of high resolution at high speed, using a multi-stage frequency synthesizer. SOLUTION: The initial stage of the frequency synthesizer is a conventional phase-locked loop connected to a dynamically variable frequency divider. There are one or more intermediate stages provided with the forward part of the phase-locked loop connected to the dynamically variable frequency divider for performing feedback through a fixed frequency divider. The final stage is provided with the forward part of the phase-locked loop connected to a different fixed frequency divider for performing feedback through the fixed frequency divider. By changing the frequency division constant of the variable frequency divider of a circuit, fine frequency adjustment is performed at a very high speed. The accuracy of the adjustment depends on the relative value of the frequency divider and the number of the intermediate stages inside a system.

147. 发明专利

JP2001510672A 失效
公开(公告)号：JP2001510672A
公开(公告)日：2001-07-31
申请号：JP53045699
申请日：1998-11-30
IPC分类号： H03L7/22 , H03D7/16 , H03J7/06 , H03L7/23 , H04B1/00 , H04B1/26 , H04B1/30 , H04B1/40

148. 发明专利

JP2000513533A 失效
公开(公告)号：JP2000513533A
公开(公告)日：2000-10-10
申请号：JP50405198
申请日：1997-06-30
IPC分类号： H03L7/12 , G01S7/02 , G01S7/282 , G01S7/35 , G01S13/34 , H03B23/00 , H03L7/07 , H03L7/22 , H03L7/23 , H04B1/26

149. 发明专利

JP2000031898A TRANSMISSION AND RECEIVING SYSTEM FOR MOBILE TELEPHONE AND TRANSMITTING METHOD 失效
公开(公告)号：JP2000031898A
公开(公告)日：2000-01-28
申请号：JP16276599
申请日：1999-06-09
申请人： ALSTHOM CGE ALCATEL
发明人： YANG FUGI , GENEST PIERRE , DUSSAUBY ERIC , BERLAND CORINE , MAECKER ARNAUD
IPC分类号： H04B7/26 , H03C3/09 , H03D7/16 , H03L7/16 , H03L7/23 , H04B1/50
摘要： PROBLEM TO BE SOLVED: To make the division coefficient of a frequency divider in a conversion frequency loop small to reduce noise and also to facilitate the movement of a frequency by adding and subtracting the frequencies of the conversion frequency loop and an intermediate frequency loop and producing a transmission frequency. SOLUTION: Phase-locked loops 1 to 3 generate about 100 MHz intermediate frequency signal 4, about 1700 MHz conversion frequency signal 5 and about 1800 MHz transmission frequency signal 6 which adds the signals 4 and 5 respectively. The loops 1 and 2 are subjected to frequency locking by means of a signal obtained by performing frequency division of a reference signal of the frequency 13 MHz of a reference circuit 12. That is, values are inputted to each phase comparator 15 and 16 of the loops 1 and 2 through frequency dividers 13 and 14 of respective Mi and Ms and the outputs of voltage controlled oscillators VCO 17 and 18 of each loop are compared with output signals of shift dividers 19 and 20 of values Ni and Ns to control the VCO. In such a case the Ni of the divider 19 is set to a small level. Also, the division coefficient of each frequency divider is programmed so as to be automatically reset to a prescribed value.

150. 发明专利

JP2000013225A OSCILLATOR 失效
公开(公告)号：JP2000013225A
公开(公告)日：2000-01-14
申请号：JP17717598
申请日：1998-06-24
申请人： HITACHI ELECTRONICS
发明人： SATO KAZUNORI
IPC分类号： H03L7/16 , H03L7/22 , H03L7/23 , H04B1/04 , H04B1/26 , H04B1/3822 , H04B1/40
摘要： PROBLEM TO BE SOLVED: To use an oscillator over a wide range without switching voltage- controlled oscillation circuits even at low frequencies by setting the oscillation frequency of the voltage-controlled oscillator higher than a necessary frequency, forming a phase-locked loop circuit, and configuring to obtain a necessary frequency signal by converting the frequency of the oscillation output of the voltage-controlled oscillator. SOLUTION: Frequencies oscillated by voltage-controlled oscillation circuits 4 and 4' in a local oscillator 1 are high frequencies which can be made broadband relatively easily and combined by a frequency converter 8 to obtain a target frequency. For example, when the target frequency is 30 MHz, the voltage-control oscillation circuit 4 generates 150 MHz, the voltage-controlled oscillation circuit 4' generates 120 MHz, and the frequency converter 8 generates 150-120=30 MHz. The variation range of the oscillation frequencies can be made wide without switching the voltage-controlled oscillation circuits even at low frequencies and the oscillator 1 is usable over a wide range.

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