专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

141. 发明授权

US6045893A Multilayered electronic part with minimum silver diffusion 失效
标题翻译：具有最小银扩散性的多层电子部件
公开(公告)号：US6045893A
公开(公告)日：2000-04-04
申请号：US75822
申请日：1998-05-12
申请人： Hideko Fukushima , Naoyuki Satoh , Hiroyuki Itoh , Tomomi Ogawa
发明人： Hideko Fukushima , Naoyuki Satoh , Hiroyuki Itoh , Tomomi Ogawa
IPC分类号： H05K1/09 , C04B35/00 , H01F17/00 , H01F17/04 , H01F41/04 , H01F41/16 , H01G4/30 , H01L23/544 , H05K1/03 , H05K3/46 , B32B3/00
CPC分类号： H01L23/544 , H01F17/0013 , H01F17/04 , H01F41/043 , H01F41/046 , H01F41/16 , H01G4/30 , H01L2223/54473 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/4611 , H05K3/4629 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
摘要： A multilayered electronic part with minimized silver diffusion into ceramic body. The multilayered electronic part is produced by sintering a green ceramic body of a plurality of ceramic layers comprising a main phase and a grain boundary phase, at least one of the ceramic layers being printed thereon Ag-containing internal electrode patterns which may serve as markers for indicating several information such as a production number, a name of manufacturer, a kind of circuit, etc. By the production method of the invention, the diffusion of Ag in the internal electrode patterns into the ceramic body is effectively prevented to avoid the deterioration of the electrical characteristics as well as to avoid the blackening of the ceramic to ensure a high lightness of the ceramic body which enhances the reliability of the visual identification and distinguishability of the markers.
摘要翻译：多层电子部件，其最小化银扩散到陶瓷体中。多层电子部件通过烧结包含主相和晶界相的多个陶瓷层的生坯陶瓷体来制造，至少一个陶瓷层被印刷在其上的含Ag内部电极图案，其可以用作表示生产编号，制造商名称，电路种类等多种信息。通过本发明的制造方法，可以有效地防止Ag在内部电极图案中扩散到陶瓷体中，以避免劣化电气特性以及避免陶瓷变黑以确保陶瓷体的高亮度，从而提高了可视化识别的可靠性和标记的可区分性。

142. 发明授权

US5987563A Flash memory accessed using only the logical address 有权
标题翻译：只能使用逻辑地址访问闪存
公开(公告)号：US5987563A
公开(公告)日：1999-11-16
申请号：US208474
申请日：1998-12-10
申请人： Hiroyuki Itoh , Noriyuki Matsui
发明人： Hiroyuki Itoh , Noriyuki Matsui
IPC分类号： G06F3/08 , G06F3/06 , G06F11/10 , G06F12/00 , G06F12/02 , G11C16/02 , G11C16/10 , G11C17/00
CPC分类号： G06F11/1068 , G06F12/02 , G06F12/0246 , G06F3/0601 , G06F3/061 , G06F3/0613 , G06F3/064 , G06F3/0652 , G06F3/0679 , G11C16/102 , G11C16/105 , G06F12/023 , G06F2003/0694
摘要： A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data.
摘要翻译：一种能够高速更新数据的闪速存储器控制装置和方法。闪速存储器控制装置包括具有存储区域的闪速存储器，该存储器区域被分成多个扇区，每个扇区各自包括用于存储扇区的逻辑地址的逻辑地址部分，擦除管理部分，用于存储至少指示是否可以擦除扇区，以及用于存储数据的数据部分; 以及耦合到闪速存储器的控制装置，用于通过指定任意扇区的逻辑地址来访问闪存的任意扇区。闪速存储器控制方法包括以下步骤：（a）将闪速存储器的存储区域划分为多个扇区; 和（b）通过指定任意扇区的逻辑地址来访问闪速存储器的任意扇区。每个扇区包括用于存储扇区的逻辑地址的逻辑地址部分，用于存储至少指示是否可以擦除扇区的信息的擦除管理部分和用于存储数据的数据部分。

143. 发明授权

US5983312A Simultaneously writing to and erasing two commonly numbered sectors 失效
标题翻译：同时写入和擦除两个常用编号的扇区
公开(公告)号：US5983312A
公开(公告)日：1999-11-09
申请号：US912692
申请日：1997-08-18
申请人： Shinpei Komatsu , Yumi Ishii , Tomohiro Hayashi , Shogo Shibazaki , Hiroyuki Itoh , Masaru Takehara
发明人： Shinpei Komatsu , Yumi Ishii , Tomohiro Hayashi , Shogo Shibazaki , Hiroyuki Itoh , Masaru Takehara
IPC分类号： G11C16/02 , G06F12/00 , G06F12/02 , G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/765 , G11C29/76 , G11C29/82
摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.
摘要翻译：从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。由上述数据更新的旧数据将被擦除或标记为擦除标志。在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。在这样做时，解码表被重写以重新排列存储器区域。

144. 发明授权

US5966720A Flash memory accessed using only the logical address 失效
标题翻译：仅使用逻辑地址访问闪存
公开(公告)号：US5966720A
公开(公告)日：1999-10-12
申请号：US998073
申请日：1997-12-24
申请人： Hiroyuki Itoh , Noriyuki Matsui
发明人： Hiroyuki Itoh , Noriyuki Matsui
IPC分类号： G06F3/08 , G06F3/06 , G06F11/10 , G06F12/00 , G06F12/02 , G11C16/02 , G11C16/10 , G11C17/00
CPC分类号： G06F11/1068 , G06F12/02 , G06F12/0246 , G06F3/0601 , G06F3/061 , G06F3/0613 , G06F3/064 , G06F3/0652 , G06F3/0679 , G11C16/102 , G11C16/105 , G06F12/023 , G06F2003/0694
摘要： A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data
摘要翻译：一种能够高速更新数据的闪速存储器控制装置和方法。闪速存储器控制装置包括具有存储区域的闪速存储器，该存储器区域被分成多个扇区，每个扇区各自包括用于存储扇区的逻辑地址的逻辑地址部分，擦除管理部分，用于存储至少指示是否可以擦除扇区，以及用于存储数据的数据部分; 以及耦合到闪速存储器的控制装置，用于通过指定任意扇区的逻辑地址来访问闪存的任意扇区。闪速存储器控制方法包括以下步骤：（a）将闪速存储器的存储区域划分为多个扇区; 和（b）通过指定任意扇区的逻辑地址来访问闪速存储器的任意扇区。每个扇区包括用于存储扇区的逻辑地址的逻辑地址部分，用于存储至少指示是否可以擦除扇区的信息的擦除管理部分和用于存储数据的数据部分

145. 发明授权

US5870289A Chip connection structure having diret through-hole connections through adhesive film and wiring substrate 失效
标题翻译：芯片连接结构具有通过粘合膜和布线基板的直通通孔连接
公开(公告)号：US5870289A
公开(公告)日：1999-02-09
申请号：US572747
申请日：1995-12-14
申请人： Masahide Tokuda , Takeshi Kato , Hiroyuki Itoh , Masayoshi Yagyu , Yuuji Fujita , Mitsuo Usami
发明人： Masahide Tokuda , Takeshi Kato , Hiroyuki Itoh , Masayoshi Yagyu , Yuuji Fujita , Mitsuo Usami
IPC分类号： H01L21/60 , H01L21/68 , H01L21/98 , H01L23/12 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/11 , H05K1/18 , H05K3/30 , H05K3/32 , H05K3/40 , H05K1/14 , H05K1/16 , H05K7/02 , H05K7/06
CPC分类号： H01L21/6836 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/0401 , H01L2224/04105 , H01L2224/16 , H01L2224/16235 , H01L2224/20 , H01L2224/24227 , H01L2224/451 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4518 , H01L2224/45184 , H01L2224/48091 , H01L2224/48227 , H01L2224/83192 , H01L2224/9202 , H01L2224/92144 , H01L2224/97 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H05K1/112 , H05K3/303 , H05K3/4007
摘要： A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.
摘要翻译：用于将集成电路芯片连接到实现高密度封装，高密度连接，高速信号传输和低成本的布线基板的结构。集成电路通过使用粘合膜的倒装芯片贴片连接到布线基板。直接通孔连接形成在连接焊盘的正下方，以穿过粘合膜和布线基板。这种直接通孔连接将连接垫直接连接到电线。由于芯片的面积和厚度减小，芯片以高密度安装，高密度输入和输出通过微小的二维连接来实现。直接连接到芯片的短线连接允许高速信号传输，并且通过应力分散来确保高可靠性。低成本的包装可以通过简单的工艺和设施来实现。

146. 发明授权

US5496498A Compensator for liquid crystal display 失效
标题翻译：液晶显示补偿器
公开(公告)号：US5496498A
公开(公告)日：1996-03-05
申请号：US357548
申请日：1994-12-16
申请人： Takehiro Toyooka , Shigeki Iida , Hiroyuki Itoh
发明人： Takehiro Toyooka , Shigeki Iida , Hiroyuki Itoh
IPC分类号： G02F1/133 , G02B5/30 , G02F1/1335 , G02F1/13363 , G02F1/136 , G02F1/1368 , C09K19/52 , G02F1/13
CPC分类号： G02F1/133636 , C09K19/0208 , C09K19/3866
摘要： A compensator for an active matrix type liquid crystal display using a thin film transistor is provided. The compensator is made by a film of a liquid crystalline polymer which exhibits a twisted nematic orientation in a liquid crystal state and assumes a glassy state at temperatures below a liquid crystal transition point thereof, the constituent molecules of the liquid crystalline polymer film having a helical structure with a helical axis wherein the twist angle is in the range of 70 to 150 degrees, and the product .DELTA.n.multidot.d of birefringence .DELTA.n of the liquid crystalline polymer film and film thickness,d, being in the range of 0.2 to 3.0 .mu.m.
摘要翻译：提供了使用薄膜晶体管的有源矩阵型液晶显示器的补偿器。补偿器由液晶聚合物膜制成，呈液晶状态的扭转向列取向，并且在低于其液晶转变点的温度下呈玻璃态，液晶聚合物膜的构成分子具有螺旋形具有螺旋轴的结构，其中扭转角在70至150度的范围内，液晶聚合物膜的双折射率DELTA n的乘积DELTA nxd和膜厚度d在0.2至3.0μm的范围内。

147. 发明授权

US5472635A Phase plate and liquid crystal display using same 失效
标题翻译：相板和液晶显示器使用相同
公开(公告)号：US5472635A
公开(公告)日：1995-12-05
申请号：US218690
申请日：1994-03-28
申请人： Shigeki Iida , Takehiro Toyooka , Hiroyuki Itoh , Yasuyuki Takiguchi , Akihiko Kanemoto , Haruo Iimura
发明人： Shigeki Iida , Takehiro Toyooka , Hiroyuki Itoh , Yasuyuki Takiguchi , Akihiko Kanemoto , Haruo Iimura
IPC分类号： G02F1/13363 , G02F1/139 , C09K19/52 , C09K19/56 , G02F1/13
CPC分类号： G02F1/13363 , C09K19/3809 , G02F1/1396 , G02F2001/133633 , G02F2413/02 , G02F2413/08 , G02F2413/13
摘要： Provided is a phase plate comprising a light transmitting base, an alignment layer formed on said base, and a film formed on said alignment layer by a liquid crystalline polymer which exhibits a nematic orientation in the state of liquid crystal and assumes a glassy state at a temperature below the liquid crystal transition point of the polymer.
摘要翻译：提供了一种相位板，其包括透光基底，在所述基底上形成的取向层，以及通过液晶聚合物形成在所述取向层上的膜，所述液晶聚合物在液晶状态下呈现向列取向，并呈现出玻璃状态温度低于聚合物的液晶转变点。

148. 发明授权

US5403783A Integrated circuit substrate with cooling accelerator substrate 失效
标题翻译：具有冷却加速器基板的集成电路基板
公开(公告)号：US5403783A
公开(公告)日：1995-04-04
申请号：US168762
申请日：1993-12-16
申请人： Keiichiro Nakanishi , Tsuneyo Chiba , Hiroyuki Itoh , Tatsuya Saitoh , Takeshi Kato
发明人： Keiichiro Nakanishi , Tsuneyo Chiba , Hiroyuki Itoh , Tatsuya Saitoh , Takeshi Kato
IPC分类号： H01L21/48 , H01L23/427 , H01L23/433 , H01L23/473 , H01L21/60
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/427 , H01L23/433 , H01L23/473 , H01L2224/16225 , H01L2224/29111 , H01L2224/73253 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01043 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/07802 , H01L2924/10329 , H01L2924/14 , H01L2924/15312 , H01L2924/16152
摘要： An electronic device includes an integrated circuit device, the integrated circuit device comprises a first substrate including an integrated electronic semiconductor circuit and a second substrate including a cooling accelerator for accelerating a heat energy exchange between the integrated electronic semiconductor circuit and a cooling fluid, and the second substrate is joined fixedly with the first substrate through a covalent bond formed between the first substrate and the second substrate.
摘要翻译：电子设备包括集成电路器件，该集成电路器件包括包括集成电子半导体电路的第一衬底和包括用于加速集成电子半导体电路和冷却流体之间的热能交换的冷却加速器的第二衬底，第二基板通过在第一基板和第二基板之间形成的共价键与第一基板固定连接。

149. 发明授权

US5396077A Electron beam lithography apparatus having electron optics correction system 失效
标题翻译：具有电子光学校正系统的电子束光刻设备
公开(公告)号：US5396077A
公开(公告)日：1995-03-07
申请号：US213737
申请日：1994-03-16
申请人： Yasunari Sohda , Hiroyuki Itoh , Yasuhiro Someda , Yoshinori Nakayama , Hidetoshi Satoh , Genya Matsuoka
发明人： Yasunari Sohda , Hiroyuki Itoh , Yasuhiro Someda , Yoshinori Nakayama , Hidetoshi Satoh , Genya Matsuoka
IPC分类号： H01L21/027 , H01J37/244 , H01J37/26 , H01J37/317 , H01J37/304
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/30455
摘要： An electron beam apparatus used in a cell projection method has a system for correcting the electron optics. A figured electron beam that has been passed through a cell having a complex figure shape is directed onto a stage on which a substrate is positioned. A fine hole is formed in the substrate and an electron detector is positioned underneath the fine hole to receive the electrons that pass through the fine hole. The output signal of the electron detector is processed to provide a representation of the degree of focus and astigmatism correction of the electron optics. When a line and space pattern is used to shape the electron beam, the output signal from the electron detector has a series of peak intensity values that, when maximized, indicate an optimum correction of the electron optics. Optionally, a limited aperture is positioned between the substrate having a fine hole and the electron detector to limit the detection of scattered electrons that have not passed through the fine hole.
摘要翻译：在电池投影方法中使用的电子束装置具有用于校正电子光学的系统。已经通过具有复杂图形形状的单元的图形电子束被引导到其上定位有基板的台上。在基板中形成细孔，电子检测器位于细孔下方，以接收穿过细孔的电子。处理电子检测器的输出信号以提供电子光学的聚焦和像散校正的表示。当使用线和空间图案来形成电子束时，来自电子检测器的输出信号具有一系列峰值强度值，当最大化时，其表示电子光学的最佳校正。可选地，有限孔被定位在具有细孔的基板和电子检测器之间，以限制未通过细孔的散射电子的检测。

150. 发明授权

US5394490A Semiconductor device having an optical waveguide interposed in the space between electrode members 失效
标题翻译：具有插入在电极构件之间的空间的光波导的半导体装置
公开(公告)号：US5394490A
公开(公告)日：1995-02-28
申请号：US104582
申请日：1993-08-11
申请人： Takeshi Kato , Yuuji Fujita , Kenichi Mizuishi , Atumi Kawata , Hiroyuki Itoh
发明人： Takeshi Kato , Yuuji Fujita , Kenichi Mizuishi , Atumi Kawata , Hiroyuki Itoh
IPC分类号： G02B6/12 , G02B6/13 , G02B6/30 , G02B6/42 , G02B6/43 , G06F1/10 , H05K1/00
CPC分类号： G02B6/43 , G02B6/13 , G02B6/30 , G02B6/42 , G06F1/105 , G02B2006/12104 , G02B6/4232 , H01L2224/16237 , H01L2224/73253 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/15312 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025
摘要： A clock signal supply system is disclosed for a semiconductor device with a semiconductor chip and a wiring substrate connected in flip-chip fashion and an optical waveguide interposed in the space between electrode members, in which the mutual arrangement of the electrical interconnection and the optical waveguide interconnection on the wiring substrate is not affected and can be used separately from each other for different applications, thereby improving the throughput of the interconnections as a whole. In order to distribute a very fast clock signal beyond a 1 GHz in particular without any phase deviation in the clock signal supply system, a clock distributor includes a clock oscillator, a phase adjuster for adjusting the phase at each destination of the clock signal, an optical interconnection for supplying the clock signal to the phase adjuster, a reference signal generator for generating a phase reference signal from the clock signal, and an electrical interconnection for supplying the reference signal to the phase adjuster. The clock signal is supplied by an optical interconnection having a broad frequency bandwidth, and the phase reference signal by an electrical interconnection by which the skew is controlled easily. A clock signal adjusted to high phase accuracy can thus be distributed to following destinations by the phase adjuster.
摘要翻译：公开了一种半导体器件的时钟信号供给系统，半导体器件具有以倒装芯片方式连接的半导体芯片和布线基板，以及插入在电极部件之间的空间中的光波导，其中电互连和光波导布线基板上的互连不受影响，并且可以彼此分开地用于不同的应用，从而提高互连的整体的吞吐量。为了在非常快的时钟信号中分配非常快的时钟信号，特别是在时钟信号供给系统中没有任何相位偏差，时钟分配器包括时钟振荡器，用于调整时钟信号的每个目的地的相位的相位调节器，用于向相位调节器提供时钟信号的光互连，用于从时钟信号产生相位参考信号的参考信号发生器和用于将参考信号提供给相位调节器的电互连。时钟信号由具有宽频带宽的光互连提供，并且相位参考信号由通过电互连的相位参考信号提供，通过该互连可以容易地控制偏斜。因此，调整到高相位精度的时钟信号可以由相位调节器分配到后续目的地。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式