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141. 发明申请

US20110136326A1 PILLAR DEVICES AND METHODS OF MAKING THEREOF 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US20110136326A1
公开(公告)日：2011-06-09
申请号：US13026381
申请日：2011-02-14
申请人： Vance DUNTON , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance DUNTON , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

142. 发明申请

US20100317145A1 SELECTIVE ETCH FOR DAMAGE AT EXFFOLIATED SURFACE 有权
标题翻译：选择性蚀刻在损伤表面的损伤
公开(公告)号：US20100317145A1
公开(公告)日：2010-12-16
申请号：US12484271
申请日：2009-06-15
申请人： Mark H. Clark , S. Brad Herner , Mohamed M. Hilali
发明人： Mark H. Clark , S. Brad Herner , Mohamed M. Hilali
IPC分类号： H01L31/18 , H01L21/30
CPC分类号： H01L21/30604 , H01L21/76254 , H01L31/028 , H01L31/068 , H01L31/1892 , Y02E10/547
摘要： Ions are implanted into a silicon donor body, defining a cleave plane. A first surface of the donor body is affixed to a receiver element, and a lamina is exfoliated at the cleave plane, creating a second surface of the lamina. There is damaged silicon at the second surface, which will compromise the efficiency of a photovoltaic cell formed from the lamina. A selective etchant, having an etch rate which is positively correlated with the concentration of structural defects in silicon, is used to remove the damaged silicon at the second surface, while removing very little of the relatively undamaged lamina.
摘要翻译：离子被植入到硅供体体内，限定了一个解理面。供体主体的第一表面固定在接受元件上，并且在分裂面上剥离薄片，形成薄片的第二表面。在第二表面有损坏的硅，这将损害由薄片形成的光伏电池的效率。使用具有与硅中的结构缺陷的浓度正相关的蚀刻速率的选择性蚀刻剂来除去第二表面处的损坏的硅，同时去除非常少的相对未损伤的层。

143. 发明申请

US20100283053A1 NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATURE 审中-公开
标题翻译：非易失性存储器阵列，包含在低温下制成的基于硅的二极管
公开(公告)号：US20100283053A1
公开(公告)日：2010-11-11
申请号：US12463530
申请日：2009-05-11
申请人： Mark H. Clark , S. Brad Herner
发明人： Mark H. Clark , S. Brad Herner
IPC分类号： H01L29/861 , H01L21/20
CPC分类号： H01L27/1021
摘要： In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.
摘要翻译：在本发明的实施例中，提供了一种形成单片三维存储器阵列的方法，所述方法包括形成包括多个存储单元的第一存储器级，每个存储单元包括多个包含铝或铜的导体，以及在每个存储单元中形成硅二极管，其中所述硅二极管形成在与所述导体相容的温度下。硅二极管可以使用例如热线化学气相沉积技术形成。还描述了其他方面。

144. 发明授权

US07816659B2 Devices having reversible resistivity-switching metal oxide or nitride layer with added metal 有权
标题翻译：具有可逆电阻率切换金属氧化物或具有添加金属的氮化物层的器件
公开(公告)号：US07816659B2
公开(公告)日：2010-10-19
申请号：US11287452
申请日：2005-11-23
申请人： S. Brad Herner , Tanmay Kumar
发明人： S. Brad Herner , Tanmay Kumar
IPC分类号： H01L29/02
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/165 , H01L45/1658 , H01L45/1675
摘要： A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a “0” or a “1”, in this resistivity state. Including additional metal atoms in a layer of such a resistivity-switching metal oxide or nitride compound decreases the current required to cause switching between resistivity states, reducing power requirements for an array of memory cells storing data in the resistivity state of such a layer. In various embodiments a memory cell may include a layer of resistivity-switching metal oxide or nitride compound with added metal formed in series with another element, such as a diode or a transistor.
摘要翻译：电阻率切换金属氧化物或氮化物层可达到至少两个稳定的电阻率状态。这种层可以用在非易失性存储单元中的状态变化元件中，在该电阻率状态下存储其数据状态，例如“0”或“1”。在这种电阻率切换金属氧化物或氮化物化合物的层中包括额外的金属原子降低了在电阻率状态之间导致切换所需的电流，从而降低了存储在这种层的电阻率状态下的数据的存储单元阵列的功率需求。在各种实施例中，存储器单元可以包括电阻率切换金属氧化物或具有与另一元件（例如二极管或晶体管）串联形成的附加金属的氮化物化合物层。

145. 发明授权

US07812404B2 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US07812404B2
公开(公告)日：2010-10-12
申请号：US11395995
申请日：2006-03-31
申请人： S. Brad Herner , Tanmay Kumar , Christopher J. Petti
发明人： S. Brad Herner , Tanmay Kumar , Christopher J. Petti
IPC分类号： H01L29/76
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HFxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HFxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

146. 发明授权

US07811916B2 Method for isotropic doping of a non-planar surface exposed in a void 有权
标题翻译：在空隙中暴露的非平面表面的各向同性掺杂的方法
公开(公告)号：US07811916B2
公开(公告)日：2010-10-12
申请号：US11610090
申请日：2006-12-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/223 , H01L21/383
CPC分类号： H01L21/2236 , H01L21/2252 , H01L27/101 , H01L27/1021
摘要： A method is described for isotropic or nearly isotropic shallow doping of a non-planar surface exposed in a void. The results of ion implantation, a common doping method, are inherently planar. Some fabrication methods and devices may require doping a surface of a non-planar feature exposed in a void, such as a trench. The feature is doped by flowing a gas which will provide the dopant over the exposed surfaces, or by exposing the surfaces to a plasma including the dopant. The feature may be a patterned feature, including a top surface and a sidewall. In a preferred embodiment, a semiconductor feature having a top surface and a sidewall is exposed in a trench formed in a dielectric, and a gas providing a p-type or n-type dopant is flowed in the trench, providing a p-type or n-type dopant to the semiconductor.
摘要翻译：描述了在空隙中暴露的非平面表面的各向同性或近似各向同性的浅掺杂的方法。离子注入的结果是一种普通的掺杂方法，它本身就是平面的。一些制造方法和装置可能需要掺杂暴露在诸如沟槽的空隙中的非平面特征的表面。该特征通过流动将在暴露表面上提供掺杂剂的气体或通过将表面暴露于包括掺杂剂的等离子体来掺杂。该特征可以是图案特征，包括顶表面和侧壁。在优选实施例中，具有顶表面和侧壁的半导体特征暴露在形成于电介质中的沟槽中，并且提供p型或n型掺杂剂的气体在沟槽中流动，提供p型或 n型掺杂剂。

147. 发明授权

US07767499B2 Method to form upward pointing p-i-n diodes having large and uniform current 有权
标题翻译：形成向上指向具有大且均匀电流的p-i-n二极管的方法
公开(公告)号：US07767499B2
公开(公告)日：2010-08-03
申请号：US11692151
申请日：2007-03-27
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/82 , H01L21/336
CPC分类号： G11C5/02 , G11C7/00 , G11C11/39 , G11C17/06 , G11C17/16 , G11C29/00 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L29/0657 , H01L29/0676 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/149
摘要： A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.
摘要翻译：公开了一种形成由沉积的硅，锗或硅 - 锗形成的向上指向的p-i-n二极管的方法。二极管具有底部重掺杂p型区域，中间固有或轻掺杂区域和顶部重掺杂n型区域。顶部重掺杂p型区掺杂砷，二极管的半导体材料与适当的硅化物，锗化物或硅化锗 - 锗化物接触结晶。当施加高于二极管的导通电压的电压时，可以形成具有优异的跨阵列电流均匀性的这种向上指向二极管的大阵列。该二极管有利地用于单片三维存储器阵列中。

148. 发明申请

US20100159630A1 METHOD FOR MAKING A PHOTOVOLTAIC CELL COMPRISING CONTACT REGIONS DOPED THROUGH A LAMINA 有权
标题翻译：用于制造包含通过层间结合的接触区域的光伏电池的方法
公开(公告)号：US20100159630A1
公开(公告)日：2010-06-24
申请号：US12339032
申请日：2008-12-18
申请人： Mohamed M. Hilali , Christopher J. Petti , S. Brad Herner
发明人： Mohamed M. Hilali , Christopher J. Petti , S. Brad Herner
IPC分类号： H01L21/18
CPC分类号： H01L31/03921 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.
摘要翻译：在本发明的方面，公开了一种形成具有相对的第一和第二表面的薄片的方法。重掺杂的接触区域从第一表面延伸到第二表面。通常，通过将半导体施主体附着到接收器元件，然后从半导体施主体分离薄层而形成薄片，其中薄片保持固定在接收器元件上。在本发明中，重掺杂的接触区域通过在切割层之前掺杂半导体施主体形成。然后制造包括层板的光伏电池。通过在接合元件接合之前形成重掺杂的接触区域并且断开，可以避免后接合高温步骤，这可能是有利的。

149. 发明申请

US20100159629A1 METHOD TO TEXTURE A LAMINA SURFACE WITHIN A PHOTOVOLTAIC CELL 有权
标题翻译：在光伏电池中纹理表面的方法
公开(公告)号：US20100159629A1
公开(公告)日：2010-06-24
申请号：US12343420
申请日：2008-12-23
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L31/0236
CPC分类号： H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/03921 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.
摘要翻译：有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。

150. 发明申请

US20100154873A1 PHOTOVOLTAIC CELL COMPRISING CCONTACT REGIONS DOPED THROUGH LAMINA 失效
标题翻译：包含通过LAMINA的CCONTACT区域的光电池
公开(公告)号：US20100154873A1
公开(公告)日：2010-06-24
申请号：US12339038
申请日：2008-12-18
申请人： Mohamed M. Hilali , Christopher J. Petti , S. Brad Herner
发明人： Mohamed M. Hilali , Christopher J. Petti , S. Brad Herner
IPC分类号： H01L31/00
CPC分类号： H01L31/03921 , H01L21/187 , H01L21/76254 , H01L31/022441 , H01L31/0682 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.
摘要翻译：在本发明的方面中，形成具有相对的第一和第二表面的层。重掺杂的接触区域从第一表面延伸到第二表面。通常，通过将半导体施主体附着到接收器元件，然后从半导体施主体分离薄层而形成薄片，其中薄片保持固定在接收器元件上。在本发明中，重掺杂的接触区域通过在切割层之前掺杂半导体施主体形成。然后制造包括层板的光伏电池。通过在接合元件接合之前形成重掺杂的接触区域并且断开，可以避免后接合高温步骤，这可能是有利的。

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