专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

131. 发明公开

EP0543517A3 A circuit detecting the position of an extreme "1" bit in a binary number 失效
标题翻译：检测二进制数“1”位的电路
公开(公告)号：EP0543517A3
公开(公告)日：1993-09-01
申请号：EP92309901.4
申请日：1992-10-29
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED
发明人： Walsh, Brendan , Dudbridge, Laura , Simpson, Richard David , Collins, David Nicholas , Moyse, Philip John
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： Apparatus for detecting the leftmost "1" bit or the rightmost "1" bit of an input number includes a binary tree of two-inputs OR-gates or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees of two-input multiplexers from the outputs of which appear the bits of a number representing the position in the input number of the leftmost "1" or the rightmost "1" bit.

132. 发明公开

EP0533337A1 Apparatus and method for resolving dependencies among a plurality of instructions within a storage device 失效
标题翻译：装置和用于在存储器装置中的多个命令当中解析相关方法。
公开(公告)号：EP0533337A1
公开(公告)日：1993-03-24
申请号：EP92307185.6
申请日：1992-08-06
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Tran, Thang Minh
IPC分类号： G06F9/38
CPC分类号： G06F7/74 , G06F5/12 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F2205/123
摘要： An apparatus and method for resolving data dependencies among a plurality of instructions within a storage device, such as a reorder buffer in a superscalar computing apparatus employing pipeline instruction processing. The storage device has a read pointer, indicating a most recently-stored instruction and has a write pointer, indicating a first-stored instruction of the plurality of instructions within the storage device.
A compare-hit circuit generates a compare-hit signal upon each concurrence of the respective source indicator in a next-to-be-dispatched instruction with the destination indicator of an earlier-stored instruction within the storage device; a first enable circuit generates a first enable signal for a first packet of instructions defined by the read pointer and the write pointer; a first comparing circuit generates a hit-enable signal for each concurrence of the compare-hit signal and the first enable signal; a second enable circuit generates a second enable signal for a second packet of instructions defined by the read pointer and the hit-enable signal; and a second comparing circuit generates the output signal for each concurrence of the second enable signal and the hit-enable signal.
摘要翻译：用于指令的存储装置内的多个中解析数据依赖性的装置和方法，检查如在超标量计算装置用人流水线指令处理的重新排序缓冲器。所述存储装置具有一个读指针，指示最近预存储的指令，并具有一个写指针，指示所述存储装置内的指令，所述多个第一存储指令。甲比较命中电路基因率时在respectivement源指示符的每个同意一个比较命中信号的下一-待调度的指令与存储装置内的较早存储的指令的目的地指示符; 第一使能电路基因率的第一对的由读指针和写指针定义的指令的第一分组使能信号; 第一比较电路基因率比较命中信号的每个同意命中使能信号和所述第一使能信号; 第二使能电路基因率的第二对的由读指针定义的指令的第二分组和命中使能信号使能信号; 和第二比较电路基因率第二的各同意的输出信号使能信号和命中使能信号。

133. 发明公开

EP0388506A2 Normalizer 失效
标题翻译： Normalisierer。
公开(公告)号：EP0388506A2
公开(公告)日：1990-09-26
申请号：EP89111101.5
申请日：1989-06-19
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Lamere, Virginia C. , Fite, Elaine H. , McKeen, Francis X.
IPC分类号： G06F7/00 , G06F7/60 , G06F9/46
CPC分类号： G06F7/74 , G06F7/607
摘要： A normalizer that identifies the bits that are set in input data and generates output signals representing the positions of the set bits in the input data. The normalizer has a device arranged to receive an n-bit signal. Each of the bits of the n-bit signal are either set or clear. The normalizer operates iteratively, and during each iteration: determines an end most set bit; generates a signal representing position information for this end most set bit; and clears the end most set bit that was identified during the immediately previous iteration. The normalizer also includes a novel bit counter that provides a count of the number of bits set in the input data.
摘要翻译：标准化器，其识别在输入数据中设置的位，并生成表示输入数据中设置位的位置的输出信号。归一化器具有被配置为接收n位信号的装置。 n位信号的每个位都被置位或清零。归一化器迭代运行，并且在每次迭代期间：确定最终设置的最后位; 产生一个信号，表示这个最终设定位的位置信息; 并清除在上一次迭代期间确定的最终位。归一化器还包括提供输入数据中设置的位数的计数的新型位计数器。

134. 发明公开

EP0328619A1 APPARATUS AND METHOD FOR USING A SINGLE CARRY CHAIN FOR LEADING ONE DETECTION AND FOR ''STICKY'' BIT CALCULATION 失效
标题翻译：装置和方法使用单个传递链为主导“ONE” -DETEKTIERUNG和“粘”比特计算。
公开(公告)号：EP0328619A1
公开(公告)日：1989-08-23
申请号：EP88907890.0
申请日：1988-08-24
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： PENG, Victor , BOWHILL, William, Johnson , GAVRIELOV, Nachem, Mosche
IPC分类号： G06F7
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49952
摘要： In a floating point addition or subtraction procedures, two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand argu ments so that the addition or subtraction procedure between the operand fractions can be performed. In order to complete the as sociated computations correctly, it is necessary to know if any of the fraction positions removed from the fraction by the shift op eration include non-zero signals, i.e., the operation referred to as computation of the "sticky" bit. The second important shift op eration occurs after the addition or subtraction of the operand fractions has taken place. The interim resulting operand fraction must be normalized, i.e., a non-zero signal is placed in the most significant operand fraction bit position and the operand expo nent argument adjusted accordingly. In order to accomplish this normalization, the position of the leading one (most significant non-zero) bit must be identified. The present invention utilizes a carry chain both for computing the "sticky" bit information and for detecting the leading one in an operand fraction.

135. 发明专利

ZA7207887B DATA PROCESSING SYSTEM 未知
公开(公告)号：ZA7207887B
公开(公告)日：1973-07-25
申请号：ZA7207887
申请日：1972-11-07
申请人： STANDARD TELEPHONES CABLES LTD
发明人： KOBUS S , JANSSENS J , ZOILE W
IPC分类号： G06F7/74 , G06F9/308 , G06F9/355 , H04Q3/545 , G06F
CPC分类号： G06F7/74 , G06F9/30018 , G06F9/355 , H04Q3/54533

136. 发明授权

KR101753162B1 이진수 연산의 선행 제로 비트수 계산방법 및, 그 장치 有权
标题翻译：用于计算二进制数运算的前导零位数的方法和设备
公开(公告)号：KR101753162B1
公开(公告)日：2017-07-04
申请号：KR1020110011214
申请日：2011-02-08
申请人： 삼성전자주식회사
发明人： 유형석
IPC分类号： G06F7/74 , G06F7/485 , G06F7/50
CPC分类号： G06F7/74 , G06F7/485 , G06F7/50
摘要： 이진수의연산시입력된피연산자에대한이진트리구조를이용하여선행제로비트수를정확하게예측하고, 피연산자의비트수증가에따른연산지연시간을줄일수 있는이진수연산의선행제로비트수계산방법및, 그장치에관한기술로써, 일실시예에따른이진수연산의선행제로비트수계산방법은입력된두 개의이진수를, 같은자릿수의비트별로논리연산하여 2의 n승개의제1 함수를생성하는단계와, 제1 함수를조합하여제2 함수및 제2 함수의선행제로비트수후보값을계산하는단계와, 계산하는단계를 n번반복하여, 최종선행제로비트수제로비트수는단계를포함한다.
摘要翻译：如何确切地一个二进制数的操作期间使用一二进制树结构对操作数输入端的零预测前的比特数，和领先的二进制运算的零个比特，根据比特数减少的操作的延迟时间的数量增加操作数的计算，并且，所述根据实施例的计算二进制数操作的前导零位数的方法包括以下步骤：通过逻辑地计算逐位输入的两个二进制数来生成两个n个第一函数，通过组合第一函数计算第二函数和第二函数的前导零比特数候选值，并且重复计算步骤n次，其中最后的前导零比特零比特数包括以下步骤：

137. 发明公开

KR1020150115872A 히트 및 멀티-히트 검출을 이용한 하이브리드 동적-정적 인코더 有权
标题翻译：混合动态静态编码器，具有HIT和多重检测功能
公开(公告)号：KR1020150115872A
公开(公告)日：2015-10-14
申请号：KR1020157023824
申请日：2014-02-06
申请人： 퀄컴 인코포레이티드
发明人： 호프,데이비드폴 , 델라로바,트레이시에이. , 마츠로프,제이슨피.
IPC分类号： G06F7/74 , G11C15/04
CPC分类号： G11C15/04 , G06F7/74 , G11C15/043 , H03K19/0013
摘要： 본명세서에서설명된하이브리드동적-정적인코더는, 완전동적인코더와비교하여동등한로직지연으로, 영역, 파워, 및누설절약들을제공하기위해동적및 정적로직을결합한다. 예를들어, 하이브리드동적-정적인코더는동일한상부절반및 하부절반을포함하고, 상부절반및 하부절반은최종인코딩된인덱스, 히트, 및멀티-히트출력들을생성하기위해결합된다. 각각의인코더절반은도팅된탐색키에매칭되는행들을갖는각각의인덱스비트에대해동적네트를이용한다. 행이탐색키에매칭됨을표시하기위해행이도팅되는경우, 그와연관된동적네트들은그 행과연관된인덱스를반영하기위해평가된다. 따라서, 하이브리드동적-정적인코더는, 인덱스, 히트, 및멀티-히트동적네트들에걸쳐리던던트풀-다운구조들을레버리징(leverage)하는더 작은동적네트들의감소된세트를갖는다.

138. 发明公开

KR1020040065810A 부동 소수점 연산을 지원하는 프로세서 无效
标题翻译：用于支持浮点计算的处理器
公开(公告)号：KR1020040065810A
公开(公告)日：2004-07-23
申请号：KR1020030002990
申请日：2003-01-16
申请人： 엘지전자 주식회사
发明人： 김효진
IPC分类号： G06F9/00
CPC分类号： G06F7/74 , G06F5/012 , G06F9/30014 , G06F9/30029 , H03M7/24
摘要： PURPOSE: A floating point calculation supporting processor is provided to perform a floating point calculation without an excessive cycle overhead. CONSTITUTION: The device comprises a program memory(11), a decoding and pipeline controller(13), a data memory(14), address generators(15, 18), and an ALU(Arithmetic and Logic Unit). The program memory(11) stores a program for a floating point calculation. The decoding and pipeline controller(13) controls blocks and pipelines for the floating point calculation by using an instruction register and a decoded program. The data memory(14) stores internal data and a calculation result. The address generators(15, 18) generate a program address and a data address. The ALU(16) determines a sign of input data, negates the input data and gets an exponent of the data in a case of a minus sign.
摘要翻译：目的：提供浮点计算支持处理器，以执行浮点计算，而不会产生过多的周期开销。构成：该装置包括程序存储器（11），解码和流水线控制器（13），数据存储器（14），地址生成器（15,18）和ALU（算术和逻辑单元）。程序存储器（11）存储用于浮点计算的程序。解码和流水线控制器（13）通过使用指令寄存器和解码程序来控制用于浮点计算的块和管线。数据存储器（14）存储内部数据和计算结果。地址发生器（15,18）产生程序地址和数据地址。 ALU（16）确定输入数据的符号，否定输入数据，并在负号的情况下获得数据的指数。

139. 发明授权

KR100382214B1 특정디지트를선행하는디지트의수를결정하는장치및방법 失效
公开(公告)号：KR100382214B1
公开(公告)日：2003-07-18
申请号：KR1019950025901
申请日：1995-08-22
申请人： 아드밴스트 마이크로 디이바이시스 인코포레이티드
发明人： 리오넬로자노
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： When a data input signal having R plus X groups of M digits is received, the digits are segmented such that X different first counter-detectors receive M digits and a second counter-detector receives the R digits. The counter-detectors determine a number of most significant count digits leading a most significant non-count digit and detect the presence of a non-count digit. A decoder receives the outputs of the first counter-detectors and, responsive to a non-count digit detection in a most significant group of M digits having a non-count digit, communicates the corresponding count number to a concatenator. A third counter-detector determines and communicates a number of most significant groups of M digits having no non-count digits. An output of the third counter detector is concatenated with an output of the decoder where the decoder output is represented by Z digits where M=N (X, M, R, N, and Z are non-negative integers). The concatenation represents the number of leading count digits. If R is non-zero, the second counter-detector determines a number of most significant count digits leading a most significant non-count digit and detects the presence of a non-count digit in the R most significant bits. An adder then adds R to the concatenation. A multiplexer selects the number of leading count digits in the R bits if the R bits contain a non-count digit else the multiplexer selects the concatenation plus R.
摘要翻译：当接收到具有R加X组M位的数据输入信号时，这些数字被分段，使得X个不同的第一反侦测器接收M个数字，而第二个反侦测器接收R个数字。反检测器确定导致最重要的非计数位数的最重要的计数位数，并检测非计数位的存在。解码器接收第一反检测器的输出，并且响应于具有非计数位的最高有效M位组中的非计数位检测，将相应的计数编号传送给连接器。第三个反检测器确定并传送不具有非计数位数的M位数的最重要组。第三计数器检测器的输出与解码器的输出连接，其中解码器输出由Z位表示，其中M = N＆lt; Z＆gt; （X，M，R，N和Z是非负整数）。连接表示前导计数位数。如果R不为零，则第二个计数器检测器确定最高有效计数位的数量，并导致最重要的非计数位，并检测R个最高有效位中是否存在非计数位。然后加法器将R添加到串联中。如果R位包含非计数位，则多路复用器选择R位中的前导计数位的数量，否则多路复用器选择级联加R。＆lt;图像＆GT;

140. 发明授权

KR100253407B1 에프오디 회로 失效
标题翻译：第一个检测器电路
公开(公告)号：KR100253407B1
公开(公告)日：2000-04-15
申请号：KR1019980002013
申请日：1998-01-23
申请人： 현대반도체 주식회사
发明人： 박성수
IPC分类号： G06F7/38
CPC分类号： G06F7/74
摘要： PURPOSE: An FOD(first-one-detector) circuit is provided to detect the reading zero rapidly by using few numbers transmission transistor when bit number of fraction inputs is increased. CONSTITUTION: A transmission transistor(Pn) transmits a fraction input 1(n) in accordance with a control signal G(n+1) outputted from previous superior bit. A transmission transistor(Pn') fixes a voltage of a node(n1) as a high level when the transmission transistor(Pn) is turned off in accordance with the control signal G(n+1). An inverter(In) reverses the voltage of a node(n1) and controls a transmission transistor(Pn-1) of the next lower bit. An AND gate(ANn) logically multiplies the fraction input 1(n) with the control signal G(n+1), and outputs the number(Z(N-1-n)) of reading zero being preceded from the most significant bit. The above 'N' denotes total bit number of the fraction input 1(n).
摘要翻译：目的：提供FOD（第一检测器）电路，通过使用少数传输晶体管，在分数输入的位数增加时快速检测读数零点。构成：发送晶体管（Pn）根据从先前的上位输出的控制信号G（n + 1）发送分数输入1（n）。当发送晶体管（Pn）根据控制信号G（n + 1）关断时，传输晶体管（Pn'）将节点（n1）的电压固定为高电平。反相器（In）反转节点（n1）的电压并控制下一个较低位的传输晶体管（Pn-1）。与门（ANn）逻辑上将分数输入1（n）与控制信号G（n + 1）相乘，并输出从最高有效位之前的读零的数（Z（N-1-n））。上述“N”表示分数输入1（n）的总位数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式