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131. 发明申请

US20110175159A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110175159A1
公开(公告)日：2011-07-21
申请号：US13120987
申请日：2009-08-25
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

132. 发明申请

US20100039865A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING THE SAME 失效
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20100039865A1
公开(公告)日：2010-02-18
申请号：US12521997
申请日：2008-01-31
申请人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
发明人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
IPC分类号： G11C16/06 , H01L29/792 , H01L21/4763
CPC分类号： H01L27/11578 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11568 , H01L27/11575 , H01L27/11582
摘要： A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.
摘要翻译：根据本发明的非易失性半导体存储器件包括：衬底; 设置在所述衬底表面上方的第一字线，所述第一字线在形成存储器单元的区域中具有板形; 设置在所述第一字线表面上方的第二字线，所述第二字线具有板形; 将第一和第二字线与驱动电路连接的多个金属布线; 以及将第一和第二字线与金属布线连接的多个触点。第一字线的接触形成在第一字线接触区域中。第二字线的接触形成在第二字线接触区域中。第一字线接触区域被提供在第一字线的被拉到第二字线接触区域的表面上。

133. 发明申请

US20080175032A1 SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20080175032A1
公开(公告)日：2008-07-24
申请号：US12018486
申请日：2008-01-23
申请人： Hiroyasu TANAKA , Ryota Katsumata , Hideaki Aochi , Masaru Kidoh , Masaru Kito , Mitsuru Sato
发明人： Hiroyasu TANAKA , Ryota Katsumata , Hideaki Aochi , Masaru Kidoh , Masaru Kito , Mitsuru Sato
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： H01L27/101 , G11C5/025 , G11C5/063 , G11C11/1655 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/224 , H01L27/228 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/147
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode connected serially to the resistance change element; and a source conductive layer spreading two-dimensionally to be connected to one ends of the plurality of memory devices.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器，包括：多个存储器件，每个存储器件具有电阻变化元件和串联连接到电阻变化元件的二极管; 以及源极传导层，二维扩展以连接到多个存储器件的一端。

134. 发明授权

US08605508B2 Non-volatile semiconductor storage device having control circuit to control voltages to select transistor for erase operation 有权
标题翻译：具有控制电路以控制电压以选择用于擦除操作的晶体管的非易失性半导体存储装置
公开(公告)号：US08605508B2
公开(公告)日：2013-12-10
申请号：US13463889
申请日：2012-05-04
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。一定的电位差是导致GIDL电流的电位差。

135. 发明授权

US08278695B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08278695B2
公开(公告)日：2012-10-02
申请号：US11898746
申请日：2007-09-14
申请人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
发明人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
IPC分类号： H01L29/76 , G11C16/04
CPC分类号： H01L27/105 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second insulating film (n is a natural number not less than 2), the first to nth electrodes being plate shaped, the first to nth electrodes being first to nth conductor layers spread in two dimensions, and a second selection transistor including a third pillar shaped semiconductor formed on the second pillar shaped semiconductor, a second gate insulating film formed around the third pillar shaped semiconductor and a second gate electrode formed around the second gate insulating film.
摘要翻译：非易失性半导体存储器件包括衬底和多个存储器串，所述存储器串包括第一选择晶体管，所述第一选择晶体管包括垂直于所述衬底形成的第一柱状半导体，围绕所述第一柱状半导体形成的第一栅极绝缘膜，以及形成在第一栅极绝缘膜周围的第一栅电极和形成在第一柱状半导体上的包括第二柱状半导体的多个存储单元，第一柱状半导体的直径大于第二柱状半导体的直径在第二柱状半导体与第一柱状半导体连接的部分处的半导体，形成在第二柱状半导体周围的第一绝缘膜，形成在第一绝缘膜周围的电荷存储层，形成在电荷周围的第二绝缘膜存储层和第一至第n电极fo 围绕第二绝缘膜（n是不小于2的自然数），第一至第n电极是板状的，第一至第n电极是第一至第n导体层在二维上扩展，第二选择晶体管包括形成在第二柱状半导体上的第三柱状半导体，围绕第三柱状半导体形成的第二栅极绝缘膜和形成在第二栅极绝缘膜周围的第二栅电极。

136. 发明授权

US07910914B2 Semiconductor memory and method for manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US07910914B2
公开(公告)日：2011-03-22
申请号：US12018486
申请日：2008-01-23
申请人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kidoh , Masaru Kito , Mitsuru Sato
发明人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kidoh , Masaru Kito , Mitsuru Sato
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , G11C5/025 , G11C5/063 , G11C11/1655 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/224 , H01L27/228 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/147
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode connected serially to the resistance change element; and a source conductive layer spreading two-dimensionally to be connected to one ends of the plurality of memory devices.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器，包括：多个存储器件，每个存储器件具有电阻变化元件和串联连接到电阻变化元件的二极管; 以及源极传导层，二维扩展以连接到多个存储器件的一端。

137. 发明授权

US07868315B2 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07868315B2
公开(公告)日：2011-01-11
申请号：US12037402
申请日：2008-02-26
申请人： Hiroyasu Tanaka , Mitsuru Sato , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hideaki Aochi
发明人： Hiroyasu Tanaka , Mitsuru Sato , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hideaki Aochi
IPC分类号： H01L29/06
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/32 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/1675
摘要： A phase change memory device including plural memory cells is disclosed. Each of the memory cells includes memory transistors and phase change film portions formed above or below the memory transistors. The phase change film portions correspond to the respective memory transistors respectively. Vias are provided in order to connect each of the memory transistor in parallel to each of the phase change film portions in each of the memory cells. The vias connect the memory cells in series to one another.
摘要翻译：公开了一种包括多个存储单元的相变存储器件。每个存储单元包括形成在存储晶体管的上方或下方的存储晶体管和相变膜部分。相变膜部分别对应于相应的存储晶体管。提供通孔，以将存储晶体管中的每一个与每个存储单元中的每个相变膜部分并联连接。通孔将存储单元串联连接。

138. 发明申请

US20100172189A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20100172189A1
公开(公告)日：2010-07-08
申请号：US12620986
申请日：2009-11-18
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
IPC分类号： G11C16/04 , G11C7/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。一定的电位差是导致GIDL电流的电位差。

139. 发明申请

US20080186771A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20080186771A1
公开(公告)日：2008-08-07
申请号：US11896261
申请日：2007-08-30
申请人： Ryota Katsumata , Masaru Kito , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kidoh , Mitsuru Sato
发明人： Ryota Katsumata , Masaru Kito , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kidoh , Mitsuru Sato
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： G11C16/24 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.
摘要翻译：在NAND型闪速存储器中，集成了沿着数据线延伸的多个存储单元单元中的第一选择晶体管的控制电极，以构成第一选择信号线，同时第二选择晶体管的控制电极被积分以构成第二选择信号线。第二选择信号线从第一选择信号线移位半个间距。

140. 发明授权

US08338882B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08338882B2
公开(公告)日：2012-12-25
申请号：US12841662
申请日：2010-07-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
摘要翻译：根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。基底包括形成在基片的表面上的基片和外围电路。堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。记忆膜包括电荷存储膜。互连设置在堆叠体的下方。互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

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