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131. 发明授权

US07173683B2 Wire for liquid crystal displays, liquid crystal displays having the same, and manufacturing methods thereof 失效
标题翻译：液晶显示器用线，其液晶显示器及其制造方法
公开(公告)号：US07173683B2
公开(公告)日：2007-02-06
申请号：US09196185
申请日：1998-11-20
申请人： Myung-Koo Hur , Chang-Oh Jeong
发明人： Myung-Koo Hur , Chang-Oh Jeong
IPC分类号： G02F1/1343 , G02F1/136
CPC分类号： G02F1/136286 , G02F2001/13629 , G02F2001/136295
摘要： A wire for a liquid crystal display has a dual-layered structure comprising a first layer made of molybdenum or molybdenum alloy, and a second layer made of molybdenum nitride or molybdenum alloy nitride. To manufacture the wire, a layer made of either a molybdenum or a molybdenum alloy, and another layer one of either a molybdenum nitride or molybdenum alloy nitride by using reactive sputtering method are deposited in sequence, and then patterned simultaneously. The target for reactive sputtering is made of either molybdenum or molybdenum alloy, and the molybdenum alloy comprises one selected from the group consisting of tungsten, chromium, zirconium, and nickel of the content ratio of 0.1 to less than 20 atm % of. The reactive gas mixture for reactive sputtering includes an argon gas and inflow amount of the nitrogen gas is at least 50% of argon gas, to minimize the etch rate of the molybdenum nitride layer or the molybdenum alloy nitride layer for ITO etchant.
摘要翻译：用于液晶显示器的线具有包括由钼或钼合金制成的第一层和由氮化钼或钼合金氮化物制成的第二层的双层结构。为了制造导线，依次沉积由钼或钼合金制成的层，以及通过使用反应溅射法的氮化钼或钼合金氮化物中的另一层，然后同时进行图案化。反应溅射的目的是由钼或钼合金制成，钼合金包含选自钨，铬，锆和镍中的一种，其含量比例为0.1至小于20atm％。用于反应溅射的反应性气体混合物包括氩气，并且氮气的流入量为氩气的至少50％，以最小化用于ITO蚀刻剂的氮化钼层或钼合金氮化物层的蚀刻速率。

132. 发明申请

US20060097265A1 Thin film transistor array panel and method for manufacturing the same 审中-公开
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060097265A1
公开(公告)日：2006-05-11
申请号：US11271143
申请日：2005-11-09
申请人： Chang-Oh Jeong , Beom-Seok Cho
发明人： Chang-Oh Jeong , Beom-Seok Cho
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L27/124 , G02F1/136227 , G02F1/136286 , G02F2001/136295 , H01L27/12
摘要： Disclosed is a thin film transistor array panel comprising an insulating substrate and a gate line formed on the insulating substrate. The gate line includes a first metal layer that contains aluminum (Al), a first cover layer formed on the gate line and a gate insulating layer formed on the cover layer. A semiconductor layer is provided on a predetermined portion of the gate insulating layer and a data line is formed on the gate insulating layer and the semiconductor layer. The semiconductor layer includes a source electrode, a drain electrode spaced apart from the source electrode by a predetermined distance. A pixel electrode connected to the electrode is provided.
摘要翻译：公开了一种薄膜晶体管阵列面板，其包括绝缘基板和形成在绝缘基板上的栅极线。栅极线包括含有铝（Al）的第一金属层，形成在栅极线上的第一覆盖层和形成在覆盖层上的栅极绝缘层。半导体层设置在栅极绝缘层的预定部分上，并且在栅极绝缘层和半导体层上形成数据线。半导体层包括源电极，与源电极隔开预定距离的漏电极。提供连接到电极的像素电极。

133. 发明申请

US20060091396A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060091396A1
公开(公告)日：2006-05-04
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

134. 发明申请

US20060076562A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060076562A1
公开(公告)日：2006-04-13
申请号：US11215067
申请日：2005-08-29
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L29/04 , H01L27/148
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地与扩散阻挡层接触并且与栅电极上的源电极相对; 以及电连接到漏电极的像素电极。

135. 发明授权

US06905917B2 Thin film transistor array panel for liquid crystal display and method for manufacturing the same 有权
公开(公告)号：US06905917B2
公开(公告)日：2005-06-14
申请号：US10112890
申请日：2002-04-01
申请人： Jean-Ho Song , Chang-Oh Jeong
发明人： Jean-Ho Song , Chang-Oh Jeong
IPC分类号： G02F1/1368 , G02F1/136 , G02F1/1362 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L29/786 , H01L29/74
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629
摘要： A method of fabricating a thin film transistor array panel for a liquid crystal display is provided. A gate line assembly is formed on an insulating substrate. The gate line assembly includes gate lines and gate electrodes connected to the gate lines. A gate insulating layer is formed on the insulating substrate having the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed, the data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines and placed adjacent to the gate electrodes, and drain electrodes placed opposite to the source electrodes with respect to the gate electrodes. A protective layer is deposited onto the insulating substrate having the data line assembly. The protective layer is patterned to form first contact holes exposing the drain electrodes. Pixel electrodes are formed on the protective layer such that the pixel electrodes are electrically connected to the drain electrodes, wherein one of the gate line assembly and the data line assembly further includes a low resistance conductive layer.

136. 发明授权

US06686606B2 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
公开(公告)号：US06686606B2
公开(公告)日：2004-02-03
申请号：US10389778
申请日：2003-03-18
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chua-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chua-Gi You
IPC分类号： H01L2904
CPC分类号： G02F1/136286 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

137. 发明授权

US06582982B2 Composition for wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
公开(公告)号：US06582982B2
公开(公告)日：2003-06-24
申请号：US09962210
申请日：2001-09-26
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L2100
CPC分类号： G02F1/1368 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

138. 发明授权

US06486494B2 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
标题翻译：配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法
公开(公告)号：US06486494B2
公开(公告)日：2002-11-26
申请号：US10035245
申请日：2002-01-04
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L2904
CPC分类号： G02F1/136286 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.
摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或半导体显示器以及Al Al层或Cr层。由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

139. 发明授权

US06380559B1 Thin film transistor array substrate for a liquid crystal display 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列基板
公开(公告)号：US06380559B1
公开(公告)日：2002-04-30
申请号：US09585427
申请日：2000-06-02
申请人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
发明人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
IPC分类号： H01L2904
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136222 , G02F2001/136231 , G02F2001/13629 , G02F2201/40 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.
摘要翻译：用于液晶显示器的薄膜晶体管衬底包括绝缘衬底和形成在衬底上的栅极线组件。栅极线组件具有双层结构，其具有相对于氧化铟锡具有良好接触特性的较低层，以及表现出低电阻特性的上层。栅极绝缘层，半导体层，接触层以及第一和第二数据线层被栅极线组件依次沉积到衬底上。图案化第一和第二数据线层以形成数据线组件，并且通过数据线组件的图案蚀刻接触层，使得接触层具有与数据线组件相同的图案。钝化层沉积到数据线组件上，并且主要在显示区域和周边区域上通过使用不同光透射掩模在钝化层上形成光致抗蚀剂图案。通过光致抗蚀剂图案蚀刻钝化层和下面的层以形成半导体图案和接触窗口。然后由氧化铟锡或氧化铟锌形成像素电极，辅助栅极焊盘和补充数据焊盘。栅极和数据线组件可以形成为单层结构。在形成像素电极之前，可以在结构化衬底上形成黑色矩阵和滤色器，并且可以在像素电极和数据线之间形成开口部分，以防止可能的短路。

140. 发明授权

US06380098B1 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
标题翻译：配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法
公开(公告)号：US06380098B1
公开(公告)日：2002-04-30
申请号：US09492830
申请日：2000-01-27
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L21302
CPC分类号： G02F1/1368 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched by using the Mo or MoW layer as a mask, to use an etch gas system such as hydrogen halide and at least one selected from CF4, CHF3, CHClF2, CH3F and C2F6 yield the good characteristics of TFT, and H2 plasma treatment can cause the characteristics of the TFT to be improved.
摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金蚀刻剂或Cr蚀刻剂蚀刻以具有平滑的锥角，并且Mo或MoW层用于显示器或半导体的布线装置以及Al层和Cr层。由于可以通过调整沉积压力来沉积Mo或MoW层以对基底施加低应力，所以可以单个MoW层自身用作布线。当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，蚀刻气体系统CF4 + O2可以防止Mo或MoW合金层的蚀刻，并且蚀刻气体SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。此外，当通过使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用蚀刻气体系统如卤化氢和选自CF 4，CHF 3，CHClF 2，CH 3 F 和C2F6产生TFT的良好特性，并且H2等离子体处理可以导致TFT的特性得到改善。

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