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131. 发明申请

US20130234315A1 STRUCTURES AND METHODS FOR DETECTING SOLDER WETTING OF PEDESTAL SIDEWALLS 有权
标题翻译：用于检测PEDESTAL SIDEWALLS焊膏浸渍的结构和方法
公开(公告)号：US20130234315A1
公开(公告)日：2013-09-12
申请号：US13414877
申请日：2012-03-08
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L22/30 , H01L22/12 , H01L23/49816 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/94 , H01L2224/0401 , H01L2224/05027 , H01L2224/0508 , H01L2224/05147 , H01L2224/05166 , H01L2224/05552 , H01L2224/05558 , H01L2224/05568 , H01L2224/05584 , H01L2224/05655 , H01L2224/11462 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13023 , H01L2224/13028 , H01L2224/13111 , H01L2224/16238 , H01L2224/81191 , H01L2224/94 , H01L2924/00013 , H01L2924/00014 , H01L2924/3841 , H01L2224/11 , H01L2924/01074 , H01L2924/00012 , H01L2924/00015 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599 , H01L2924/01047 , H01L2924/01029
摘要： Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.
摘要翻译：用于检测基座侧壁焊料润湿的结构和方法。该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

132. 发明授权

US08513814B2 Buffer pad in solder bump connections and methods of manufacture 有权
标题翻译：焊料缓冲焊盘连接和制造方法
公开(公告)号：US08513814B2
公开(公告)日：2013-08-20
申请号：US13098816
申请日：2011-05-02
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02126 , H01L2224/02141 , H01L2224/02145 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05664 , H01L2224/061 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/131 , H01L2224/141 , H01L2224/14104 , H01L2924/00014 , H01L2924/01029 , H01L2924/01074 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
摘要： Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.
摘要翻译：结构提供有用于焊料凸块的凸起缓冲垫。还提供了用于形成用于焊料凸块的凸起缓冲垫的方法。该方法包括在焊料凸块连接的最后金属层的拉伸侧上形成升高的局部缓冲垫结构。凸起的局部缓冲垫结构相对于最后一个金属层的压缩侧增加焊料凸块连接的焊盘结构的一部分的高度。

133. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

134. 发明授权

US08450168B2 Ferro-electric capacitor modules, methods of manufacture and design structures 有权
标题翻译：铁电电容器模块，制造方法和设计结构
公开(公告)号：US08450168B2
公开(公告)日：2013-05-28
申请号：US12823728
申请日：2010-06-25
申请人： Jeffrey P. Gambino , Matthew D. Moon , William J. Murphy , James S. Nakos , Paul W. Pastel , Brett A. Philips
发明人： Jeffrey P. Gambino , Matthew D. Moon , William J. Murphy , James S. Nakos , Paul W. Pastel , Brett A. Philips
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L28/55 , H01L27/11507
摘要： Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.
摘要翻译：铁电电容器模块，制造方法和设计结构。制造铁电电容器的方法包括在CMOS结构的绝缘体层上形成阻挡层。该方法还包括在阻挡层上形成顶板和底板。该方法还包括在顶板和底板之间形成铁电材料。该方法还包括用封装材料封装阻挡层，顶板，底板和铁电材料。该方法还包括通过封装材料形成与顶板和底板的接触。至少与顶板的接触和与CMOS结构的扩散的接触通过公共导线电连接。

135. 发明申请

US20130084476A1 FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY 有权
标题翻译：三维固态电池的保险丝
公开(公告)号：US20130084476A1
公开(公告)日：2013-04-04
申请号：US13252366
申请日：2011-10-04
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01M10/42 , H01M10/04
CPC分类号： H01M10/04 , H01M2/204 , H01M2/24 , H01M2/34 , H01M4/767 , H01M10/02 , H01M10/052 , H01M10/0562 , H01M10/42 , Y02E60/12 , Y10T29/49108
摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.
摘要翻译：提供了具有形成在基板中的多个电池单元的固态电池结构，其制造方法和设计结构。电池结构包括形成在基板上并构造成形成电池单元的多个子阵列的图案化阴极电极层。电池结构还包括构造成互连至少两个相邻子阵列的多个熔丝。多个熔丝中的至少一个被构造成被吹塑以断开具有缺陷子阵列的互连。有利的是，多个熔丝是电池结构的组成部分。

136. 发明申请

US20130062769A1 Microstructure Modification in Copper Interconnect Structures 有权
标题翻译：铜互连结构中的微结构修改
公开(公告)号：US20130062769A1
公开(公告)日：2013-03-14
申请号：US13232085
申请日：2011-09-14
申请人： Cyril Cabral, JR. , Takeshi Nogami , Jeffrey P. Gambino , Qiang Huang , Kenneth P. Rodbell
发明人： Cyril Cabral, JR. , Takeshi Nogami , Jeffrey P. Gambino , Qiang Huang , Kenneth P. Rodbell
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L21/7684 , H01L21/2885 , H01L21/76841 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53238 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.
摘要翻译：金属互连结构和金属互连结构的制造方法。锰（Mn）被掺入到铜（Cu）互连结构中，以便在90nm以下的技术中改变微观结构以实现竹型晶界。优选地，竹颗粒在小于Blech长度的距离处分离，使得避免通过晶界的铜（Cu）扩散。添加的Mn还触发Cu颗粒向金属线底部的生长，从而形成达到底面的真正的竹结构，消除沿着金属线长度取向的晶界的Cu扩散机理。

137. 发明授权

US08373275B2 Fine pitch solder bump structure with built-in stress buffer 有权
标题翻译：具有内置应力缓冲器的细间距焊料凸块结构
公开(公告)号：US08373275B2
公开(公告)日：2013-02-12
申请号：US12021321
申请日：2008-01-29
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/485
CPC分类号： H01L24/11 , H01L2224/02125 , H01L2224/02126 , H01L2224/0401 , H01L2224/05572 , H01L2224/10126 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing.
摘要翻译：具有用于电子封装中的内置应力缓冲器的细间距焊料凸块结构以及具有内置应力缓冲器的细间距焊料凸块结构的制造方法。采用非常厚的最终钝化层，其由作为UBM（BLM）焊盘和焊料材料的最小厚度的所谓的缓冲层的聚酰亚胺构成，同时完全分离得到的聚酰亚胺岛，使得聚酰亚胺材料提供大部分物理高度用于修改C4（可控崩溃芯片连接）结构的对立。在采用聚酰亚胺材料作为垂直芯片封装互连的主要结构部件时，通过有效降低芯片制造加工步骤中遇到的高应力，可以充分利用聚酰亚胺材料的固有应力缓冲性能，作为芯片连接，回流，预处理和可靠性热循环应力。

138. 发明申请

US20130009312A1 INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING 审中-公开
标题翻译：互连结构在没有干等离子体处理的情况下制成
公开(公告)号：US20130009312A1
公开(公告)日：2013-01-10
申请号：US13603017
申请日：2012-09-04
申请人： Maxime Darnon , Jeffrey P. Gambino , Elbert E. Huang , Qinghuang Lin
发明人： Maxime Darnon , Jeffrey P. Gambino , Elbert E. Huang , Qinghuang Lin
IPC分类号： H01L23/485 , H05K1/09 , H05K1/02
CPC分类号： H01L23/53295 , H01L21/4846 , H01L21/76808 , H01L21/76834 , H01L21/76849 , H01L23/49894 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2221/1031 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.
摘要翻译：微电子结构内的互连结构和用于在微电子结构内制造互连结构的方法使用可显影底部抗反射涂层和位于其上的至少一个可成像的层间电介质层，该基底包括基底电介质层和第一导体层，其位于并形成为嵌入在所述基极介质层内。使用可显影底部抗反射涂层和至少一个可成像的层间电介质层的事件可以通过至少一个可成像的层间间隔形成孔，例如但不限于双镶嵌孔，介电层和可显影的抗反射涂层，以在位于和形成在第一导体层上时露出覆盖层，当在微电子结构内形成互连结构时，不使用干等离子体蚀刻方法。

139. 发明授权

US08299568B2 Damage propagation barrier 有权
标题翻译：损伤传播障碍
公开(公告)号：US08299568B2
公开(公告)日：2012-10-30
申请号：US13028332
申请日：2011-02-16
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/58
CPC分类号： H01L23/5258 , H01L23/5254 , H01L23/5256 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.
摘要翻译：导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。

140. 发明授权

US08232215B2 Spacer linewidth control 有权
标题翻译：间隔线宽控制
公开(公告)号：US08232215B2
公开(公告)日：2012-07-31
申请号：US12622557
申请日：2009-11-20
申请人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
摘要翻译：用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻的部分蚀刻的间隔材料层。用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

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