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131. 发明申请

US20080049834A1 Sub-block transform coding of prediction residuals 有权
标题翻译：预测残差的子块变换编码
公开(公告)号：US20080049834A1
公开(公告)日：2008-02-28
申请号：US11890059
申请日：2007-08-03
申请人： Thomas Holcomb , Chih-Lung Lin
发明人： Thomas Holcomb , Chih-Lung Lin
IPC分类号： H04N11/02
CPC分类号： H04N19/523 , G06T3/40 , G06T7/0012 , H04N19/105 , H04N19/115 , H04N19/117 , H04N19/119 , H04N19/122 , H04N19/124 , H04N19/129 , H04N19/132 , H04N19/136 , H04N19/137 , H04N19/146 , H04N19/147 , H04N19/15 , H04N19/154 , H04N19/172 , H04N19/176 , H04N19/18 , H04N19/182 , H04N19/46 , H04N19/50 , H04N19/513 , H04N19/52 , H04N19/527 , H04N19/533 , H04N19/547 , H04N19/57 , H04N19/59 , H04N19/593 , H04N19/61 , H04N19/625 , H04N19/63 , H04N19/70 , H04N19/80 , H04N19/82 , H04N19/86 , H04N19/895
摘要： Techniques and tools for sub-block transform coding are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. The encoder and decoder may use different scan patterns for different transform sizes when scanning values from two-dimensional blocks into one-dimensional arrays, or vice versa. The encoder and decoder may use sub-block pattern codes to indicate the presence or absence of information for the sub-blocks of particular blocks.
摘要翻译：描述了用于子块变换编码的技术和工具。例如，当编码8×8预测残差块时，视频编码器自适应地在8×8,8×4和4×8DCT之间切换; 相应的视频解码器在解码期间在8×8,8×4和4×8个逆DCT之间切换。视频编码器可以在不同的变换大小和切换级别的闭环评估中确定变换大小以及切换级别（例如，帧，宏块或块）。当将来自二维块的值扫描成一维阵列时，编码器和解码器可以使用不同的扫描图案用于不同的变换大小，反之亦然。编码器和解码器可以使用子块模式码来指示特定块的子块的信息的存在或不存在。

132. 发明申请

US20080018568A1 Organic Light-Emitting Diode (OLED) Panel and Driving Method Thereof 有权
标题翻译：有机发光二极管（OLED）面板及其驱动方法
公开(公告)号：US20080018568A1
公开(公告)日：2008-01-24
申请号：US11739777
申请日：2007-04-25
申请人： Yung-Chih Chen , Chih-Lung Lin , Yuan-Chun Wu
发明人： Yung-Chih Chen , Chih-Lung Lin , Yuan-Chun Wu
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2300/0465 , G09G2300/0819 , G09G2300/0842 , G09G2300/0876
摘要： An organic light-emitting diode (OLED) panel and driving method thereof is provided. The OLED panel includes a plurality of data lines, scan lines, pixels, sampling voltage lines and compensation voltage lines. The sampling voltage line transmits a compensation voltage in response to compensation signals from the data lines, threshold voltages of driving transistors and organic light emitting diodes in the pixels connected to the same scan line. The corresponding compensation voltage line adjusts data signals transmitted into the pixels connected to the same scan line in response to the compensation voltage.
摘要翻译：提供一种有机发光二极管（OLED）面板及其驱动方法。 OLED面板包括多条数据线，扫描线，像素，采样电压线和补偿电压线。采样电压线响应于来自数据线的补偿信号，连接到同一扫描线的像素中的驱动晶体管和有机发光二极管的阈值电压传输补偿电压。相应的补偿电压线响应于补偿电压来调整发送到连接到相同扫描线的像素的数据信号。

133. 发明申请

US20070237232A1 Dynamic selection of motion estimation search ranges and extended motion vector ranges 有权
标题翻译：运动估计搜索范围和扩展运动矢量范围的动态选择
公开(公告)号：US20070237232A1
公开(公告)日：2007-10-11
申请号：US11400051
申请日：2006-04-07
申请人： Cheng Chang , Chih-Lung Lin , Thomas Holcomb
发明人： Cheng Chang , Chih-Lung Lin , Thomas Holcomb
IPC分类号： H04N11/02 , H04N7/12
CPC分类号： H04N19/192 , H04N19/51
摘要： Techniques and tools for selecting search ranges and/or motion vector ranges during motion estimation are described. For example, a video encoder performs motion estimation constrained by a first search range, which results in multiple motion vectors. The encoder computes motion vector distribution information for the motion vectors. To compute the distribution information, the encoder can track the motion vectors in a histogram and count how many of the motion vectors fall within each of multiple intervals for the distribution information. The encoder then selects a second search range and performs motion estimation constrained by the second search range. Selecting the second search range can include selecting a motion vector range, which in some cases in effect determines the second search range.
摘要翻译：描述了在运动估计期间选择搜索范围和/或运动矢量范围的技术和工具。例如，视频编码器执行由第一搜索范围约束的运动估计，其导致多个运动矢量。编码器计算运动矢量的运动矢量分布信息。为了计算分布信息，编码器可以跟踪直方图中的运动矢量，并计算多少个运动矢量落在分布信息的多个间隔的每一个中。然后，编码器选择第二搜索范围并执行受第二搜索范围约束的运动估计。选择第二搜索范围可以包括选择运动矢量范围，其在某些情况下有效地确定第二搜索范围。

134. 发明申请

US20070020953A1 Method for forming a high density dielectric film by chemical vapor deposition 有权
标题翻译：通过化学气相沉积法形成高密度电介质膜的方法
公开(公告)号：US20070020953A1
公开(公告)日：2007-01-25
申请号：US11186353
申请日：2005-07-21
申请人： Cheng-Yuan Tsai , Chih-Lung Lin , You-Hua Chou
发明人： Cheng-Yuan Tsai , Chih-Lung Lin , You-Hua Chou
IPC分类号： H01L21/31 , C23C8/00 , H01L21/469
CPC分类号： H01L21/31612 , C23C16/45523 , C23C16/45557 , C23C16/50 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/76801
摘要： A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)˜(d) are repeated until a high density dielectric film is formed on the substrate.
摘要翻译：一种通过化学气相沉积法形成高密度电介质膜的方法。该方法包括：（a）在处理室中设置基板; （b）第一气体以第一压力被引入处理室并吸附在衬底上，其中第一气体包含含硅或含碳气体; （c）第一气体停止，第一压力降低到第二压力; （d）第二气体以第三压力被引入处理室，并被迫与吸收在基板上的第一气体反应并保留在处理室中，其中第二气体包括氧化剂或还原剂; （e）重复步骤（b）〜（d），直到在基板上形成高密度电介质膜。

135. 发明授权

US07145172B2 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US07145172B2
公开(公告)日：2006-12-05
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： H01L31/0376 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

136. 发明授权

US07127114B2 Coded block pattern encoding with spatial prediction 有权
标题翻译：具有空间预测的编码块模式编码
公开(公告)号：US07127114B2
公开(公告)日：2006-10-24
申请号：US11323034
申请日：2005-12-30
申请人： Chih-Lung Lin , Ming-Chieh Lee
发明人： Chih-Lung Lin , Ming-Chieh Lee
IPC分类号： G06K9/36
CPC分类号： H04N19/20 , H04N19/157 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/186 , H04N19/196 , H04N19/197 , H04N19/46 , H04N19/463 , H04N19/51 , H04N19/593 , H04N19/61 , H04N19/70
摘要： The coded block parameters used to code blocks of image samples into structures called macroblocks are compressed more efficiently by exploiting the correlation between chrominance and luminance blocks in each macroblock. In particular, the coded block pattern for chrominance and luminance are combined into a single parameter for the macroblock and jointly coded with a single variable length code. To further enhance coding efficiency, the spatial coherence of coded block patterns can be exploited by using spatial prediction to compute predicted values for coded block pattern parameters.
摘要翻译：通过利用每个宏块中的色度和亮度块之间的相关性，将用于将图像样本的块编码为被称为宏块的结构的编码块参数被更有效地压缩。特别地，用于色度和亮度的编码块图案被组合成用于宏块的单个参数，并且用单个可变长度码共同编码。为了进一步提高编码效率，可以通过使用空间预测来计算编码块模式参数的预测值来利用编码块模式的空间相干性。

137. 发明申请

US20050037533A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050037533A1
公开(公告)日：2005-02-17
申请号：US10934014
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在氮化硅层上形成未掺杂的非晶硅层，ii）在未掺杂的非晶硅层上形成蚀刻掩模，以及iii）在未掺杂的非晶硅的部分上形成两个掺杂非晶硅层层和蚀刻掩模，两个掺杂的非晶硅层间隔开并位于栅极的任一侧，其中在电介质层上的未掺杂和掺杂的非晶硅层的蚀刻选择率不小于约5.0。

138. 发明申请

US20050032263A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050032263A1
公开(公告)日：2005-02-10
申请号：US10934242
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

139. 发明申请

US20050023533A1 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US20050023533A1
公开(公告)日：2005-02-03
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L29/04
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

140. 发明授权

US06338668B1 In-line chemical mechanical polish (CMP) planarizing method employing interpolation and extrapolation 有权
标题翻译：采用插值和外插法的在线化学机械抛光（CMP）平面化方法
公开(公告)号：US06338668B1
公开(公告)日：2002-01-15
申请号：US09639864
申请日：2000-08-16
申请人： Chih-Lung Lin , Wen-Cheng Chien
发明人： Chih-Lung Lin , Wen-Cheng Chien
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B37/042 , B24B49/03
摘要： Within a chemical mechanical polish (CMP) method there is first provided a first control substrate, a first series of product substrates and a second control substrate. There is then sequentially chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the first control substrate to provide a planarized first control substrate, the first series of product substrates to provide a planarized first series of product substrates and the second control substrate to provide a planarized second control substrate. There is then determined, for the planarized first control substrate and the planarized second control substrate, a corresponding first value of a parameter within the chemical mechanical polish (CMP) planarizing method and a corresponding second value of the parameter within the chemical mechanical polish (CMP) planarizing method. There may then be interpolated or extrapolated from the first value of the parameter and the second value of the parameter to provide an interpolated value of the parameter for a planarized first product substrate within the planarized first series of product substrates or an extrapolated value of the parameter which may be employed for planarizing with enhanced uniformity a second product substrate within a second series of product substrates.
摘要翻译：在化学机械抛光（CMP）方法中，首先提供第一控制基板，第一系列产品基板和第二控制基板。然后依次进行化学机械抛光（CMP）平面化，同时采用化学机械抛光（CMP）平面化方法，第一控制基板提供平面化的第一控制基板，第一系列产品基板提供平面化的第一系列产品基板和第二控制基板，以提供平坦化的第二控制基板。然后，对于平坦化的第一控制基板和平坦化的第二控制基板，确定在化学机械抛光（CMP）平面化方法内的参数的对应的第一值和化学机械抛光（CMP）内的参数的对应的第二值）平面化方法。然后可以从参数的第一值和参数的第二值进行内插或外插，以提供平面化的第一系列产品基板内的平面化第一产品基板的参数的内插值，或参数的外推值其可以用于在第二系列产品基底内以均匀化的平面化第二产品基底。

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