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121. 发明申请

US20020064072A1 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode 失效
标题翻译：可操作的同步半导体存储器件在单数据速率模式和双数据速率模式之间切换
公开(公告)号：US20020064072A1
公开(公告)日：2002-05-30
申请号：US10025857
申请日：2001-12-26
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Tsukasa Ooishi , Masatoshi Ishikawa
IPC分类号： G11C005/00
CPC分类号： G11C7/1045 , G11C7/1072
摘要： A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.
摘要翻译：同步半导体存储器件以单个数据速率SDRAM操作模式与外部时钟信号同步地操作输入/输出缓冲器电路。在双数据速率SDRAM操作模式中，产生频率为外部时钟信号的两倍的内部时钟信号。输入/输出缓冲电路与内部时钟信号同步工作。

122. 发明申请

US20020059003A1 System, method and computer program product for mapping data of multi-database origins 有权
标题翻译：用于映射多数据库起源数据的系统，方法和计算机程序产品
公开(公告)号：US20020059003A1
公开(公告)日：2002-05-16
申请号：US09816547
申请日：2001-03-26
发明人： Joseph D. Ruth , Susan A. Dorr , Nick Galemmo , Jeffrey A. Junak , Olivier Libouban , Justin O. Neway
IPC分类号： G05B019/18 , G05B011/01 , G06F007/00 , G06F017/30 , G11C005/00
CPC分类号： G06F17/30893 , Y10S707/956 , Y10S707/99934 , Y10S707/99943 , Y10S707/99945
摘要： The present invention provides a method for analyzing a process based on displaying data to a user from a plurality of different sources and a machine-readable medium for implementing such a method. The present invention also provides a mapping system and a method for displaying data to a user employing a hierarchy including data nodes and data leaves.
摘要翻译：本发明提供了一种用于基于从多个不同的源向用户显示数据以及用于实现这种方法的机器可读介质来分析过程的方法。本发明还提供了一种映射系统和一种用于向使用包括数据节点和数据树叶的层次的用户显示数据的方法。

123. 发明申请

US20020054532A1 Semiconductor memory device having function of supplying stable power supply voltage 失效
公开(公告)号：US20020054532A1
公开(公告)日：2002-05-09
申请号：US10036512
申请日：2002-01-07
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Tsukasa Ooishi , Jun Setogawa
IPC分类号： G11C005/00
CPC分类号： G11C11/4074 , G11C5/143 , G11C5/147
摘要： The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.

124. 发明申请

US20020054531A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20020054531A1
公开(公告)日：2002-05-09
申请号：US09978594
申请日：2001-10-18
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Rie Aruga
IPC分类号： G11C005/00 , H01L029/76 , H01L029/94
CPC分类号： G11C16/12 , G11C5/145 , G11C8/12 , G11C16/30 , G11C2216/16
摘要： A non-volatile semiconductor memory device includes a first memory bank, a second memory bank, a first power supply circuit, and a second power supply circuit. In write operation, the first power supply circuit supplies a boosted voltage to the first memory bank, and the second power supply circuit supplies a boosted voltage to the second memory bank. This enables sufficient current supply capability to be assured. On the other hand, in read operation, only the second power supply circuit supplies a boosted voltage to the first and second memory banks. This enables reduction in power consumption.
摘要翻译：非挥发性半导体存储器件包括第一存储体，第二存储体，第一电源电路和第二电源电路。在写入操作中，第一电源电路将升压电压提供给第一存储体，并且第二电源电路向第二存储体提供升压电压。这使得能够确保足够的电流供应能力。另一方面，在读取操作中，只有第二电源电路向第一和第二存储体提供升压电压。这能够降低功耗。

125. 发明申请

US20020054517A1 Sequence circuit and semiconductor device using sequence circuit 有权
标题翻译：序列电路和半导体器件采用顺序电路
公开(公告)号：US20020054517A1
公开(公告)日：2002-05-09
申请号：US09984270
申请日：2001-10-29
申请人： Fujitsu Limited & Kabushiki Kaisha Toshiba
发明人： Atsushi Takeuchi , Masaharu Wada
IPC分类号： G11C005/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A semiconductor device includes a word line that is reset to a negative voltage when the word line is unselected. The semiconductor device further includes a sequence circuit that clamps the word line to a first fixed voltage, until a fixed power-supply voltage that is supplied to a memory cell connected to the word line reaches a second fixed voltage, at a time of starting power supply. Thus, the semiconductor device can prevent a negative power-supply voltage used for resetting the word line from rising, and can reduce consumed energy.
摘要翻译：半导体器件包括当字线未被选择时被重置为负电压的字线。半导体器件还包括将字线夹持到第一固定电压的顺序电路，直到提供给连接到字线的存储单元的固定电源电压达到第二固定电压时，在启动电源时供应。因此，半导体器件可以防止用于复位字线的负电源电压上升，并且可以减少消耗的能量。

126. 发明申请

US20020054516A1 Semiconductor device 有权
公开(公告)号：US20020054516A1
公开(公告)日：2002-05-09
申请号：US10023891
申请日：2001-12-21
申请人： Hitachi, Ltd.
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C005/00
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.

127. 发明申请

US20020054513A1 Method for program revise of an IC smartcard system 审中-公开
标题翻译： IC智能卡系统程序修改方法
公开(公告)号：US20020054513A1
公开(公告)日：2002-05-09
申请号：US09950421
申请日：2001-09-12
发明人： Yan-Shun Kao
IPC分类号： G11C007/00 , G11C005/00
CPC分类号： G07F7/1008 , G06F8/60 , G06Q20/3552 , Y02D10/42
摘要： A method for modifying program in EEPROM of an IC smart card system. First, save the operating program of IC smart card system in a ROM, the operating program has a function of Add Command. Next, increase the content of the command code before formatting the IC smart card, wherein the increased command code and the actual content are saved in an EEPROM. Then, formatting the IC smart card to define the file segment of the EEPROM, and finally input personal data in the IC card to complete the card activating procedure. By using the program modification method, the time for the IC card producing is reduced and the efficiency is improved when there are small changes of the functions of the IC card.
摘要翻译：一种在IC智能卡系统的EEPROM中修改程序的方法。首先，将IC智能卡系统的操作程序保存在ROM中，操作程序具有Add Command功能。接下来，在格式化IC智能卡之前增加命令代码的内容，其中将增加的命令代码和实际内容保存在EEPROM中。然后，格式化IC智能卡以定义EEPROM的文件段，最后在IC卡中输入个人数据，完成卡的激活过程。通过使用程序修改方法，当IC卡的功能变化小时，IC卡产生的时间减少，并且提高效率。

128. 发明申请

US20020051400A1 Semiconductor integrated circuit device and method of manufacturing thereof 失效
公开(公告)号：US20020051400A1
公开(公告)日：2002-05-02
申请号：US09971371
申请日：2001-10-03
发明人： Kazuhide Yoneya , Masaru Koyanagi
IPC分类号： G11C005/00
CPC分类号： G11C17/18 , G11C7/1045 , G11C17/16 , G11C29/023 , G11C29/028
摘要： A semiconductor integrated circuit device comprises an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of the transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.

129. 发明申请

US20020048208A1 Semiconductor device, refreshing method thereof, memory system, and electronic instrument 失效
标题翻译：半导体器件，刷新方法，存储器系统和电子仪器
公开(公告)号：US20020048208A1
公开(公告)日：2002-04-25
申请号：US09972053
申请日：2001-10-09
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/00 , G11C008/00 , G11C005/00
CPC分类号： G11C11/406 , G11C8/12 , G11C8/18
摘要： A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for all the remaining blocks. A refresh cycle in a power saving state is caused to be longer than a refresh cycle in an operating state.
摘要翻译：一种刷新诸如VSRAM的半导体器件的方法。半导体器件1的存储单元阵列20被划分为由块A，块B，块C和块D组成的四个块。在对其中一个块进行数据读取或写入操作的时段期间，刷新对所有剩余的块执行。导致省电状态的刷新周期比操作状态下的刷新周期长。

130. 发明申请

US20020041524A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20020041524A1
公开(公告)日：2002-04-11
申请号：US09971227
申请日：2001-10-04
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C005/00
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor integrated circuit including a logic circuit having an insulated gate field effect transistor (IGFET) (352) with a reduced threshold voltage that may compensate for a reduced voltage supply is provided. The IGFET may receive a signal line (340) at a gate terminal and may provide a controllable impedance path between a signal line (320) and a node (ND). The logic circuit may include a stand-by mode in which the IGFET (352) may receive a potential at a source electrode that may be approximately equal to the potential at a drain electrode. In this way, leakage current may be reduced.
摘要翻译：提供一种半导体集成电路，其包括具有可补偿降低的电压电源的具有降低的阈值电压的绝缘栅极场效应晶体管（IGFET）（352）的逻辑电路。 IGFET可以在栅极端处接收信号线（340），并且可以在信号线（320）和节点（ND）之间提供可控阻抗路径。逻辑电路可以包括待机模式，其中IGFET（352）可以在源电极处接收可能近似等于漏电极处的电位的电位。以这种方式，泄漏电流可能会降低。

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