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121. 发明授权

US06326674B1 Integrated injection logic devices including injection regions and tub or sink regions 有权
标题翻译：集成注入逻辑器件，包括注入区域和槽或汇点区域
公开(公告)号：US06326674B1
公开(公告)日：2001-12-04
申请号：US09451623
申请日：1999-11-30
申请人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
发明人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
IPC分类号： H01L29735
CPC分类号： H01L21/8226 , H01L21/8224 , H01L21/8228 , H01L21/82285 , H01L27/0233 , H01L27/0647 , H01L27/0826
摘要： A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.
摘要翻译：公开了具有横向npn双极晶体管，垂直和横向pnp双极晶体管，集成注入逻辑，扩散电容器，多晶硅电容器和多晶硅电阻器的互补双极晶体管。横向pnp双极晶体管具有包括高密度区域和低密度区域的发射极区域和集电极区域，并且发射极区域形成在n型槽区域中。在集成注入逻辑电路中，集电极区域被高密度p型区域包围，在集电极区域形成低密度p型区域。扩散电容器和多晶硅电容器形成在一个衬底中。在形成多晶硅电阻器之前形成除了将多晶硅电阻器中的杂质扩散到外延层中形成的区域之外的扩散区域，并且多晶硅电极与多晶硅电阻器一起形成。

122. 发明授权

US5776814A Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
标题翻译：在形成第二多晶硅层之后掺杂两层双极晶体管的工艺
公开(公告)号：US5776814A
公开(公告)日：1998-07-07
申请号：US775360
申请日：1997-01-03
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732
CPC分类号： H01L27/0826 , H01L21/8228 , H01L27/082
摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device. Each device is then doped with the second type impurity through the second mask. The use of the high diffusion coefficient layer in the base contact enables the base dopant to spread laterally from the edge contact to the region where the base poly is in contact with the collector, with the same diffusion cycle that is used for the emitter.
摘要翻译：减少的掩模组，用于制造（高频应用）互补双极晶体管结构的植入复杂度过程使用材料层的快速横向扩散特性，其比发射体掺杂物比单晶半导体材料高至少一个数量级。单独的基极和发射极多晶层形成为未掺杂的。然后，一个器件的发射极多晶硅和另一个器件的基极聚合物的边缘通过掺杂剂掩模曝光并同时掺杂。发射极掺杂剂直接进入发射极聚合物的表面，其位于其上并与基底接触。基极接触掺杂剂进入基极聚合物的边缘，包括具有高扩散系数的材料层，在该层上横向扩散，然后扩散到收集器材料（例如岛）表面中，以形成外部基极。图案化第二掩模以暴露第二器件的发射极和第一器件的基极poly的边缘。然后每个器件通过第二掩模掺杂第二类型杂质。在基极接触中使用高扩散系数层使得基底掺杂剂从边缘接触侧向扩散到与聚集体接触的区域，具有与用于发射极的相同的扩散循环。

123. 发明授权

US5629219A Method for making a complementary bipolar transistor 失效
标题翻译：制造互补双极晶体管的方法
公开(公告)号：US5629219A
公开(公告)日：1997-05-13
申请号：US520704
申请日：1995-08-29
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L21/265
CPC分类号： H01L21/8228
摘要： A hole in the site for the emitter layer of the npn transistor of a complementary bipolar transistor is made in a step independent from a step of making a hole in the site for the emitter layer of the pnp transistor, and an n.sup.+ -type polycrystalline Si film doped with an n-type impurity upon being made is used to make the emitter electrode of the npn transistor. Independently from this step, a p.sup.+ -type polycrystalline Si film doped with a p-type impurity upon being made is used to make the emitter electrode of the pnp transistor. The n-type impurity diffusing from the emitter electrode makes an n.sup.+ -type emitter layer of the npn transistor, whereas the p-type impurity diffusing from the emitter electrode makes a p.sup.+ -type emitter layer of the pnp transistor. Thus the method can produce complementary bipolar transistors with a higher performance, and is suitable for combination with a process for fabricating sub-half-micron bipolar CMOSs.
摘要翻译：在互补双极晶体管的npn晶体管的发射极层的位置中的一个孔是独立于在pnp晶体管的发射极层的位置上形成空穴的步骤，并且n +型多晶Si 在制造时掺杂有n型杂质的薄膜用于制造npn晶体管的发射极。独立于该步骤，使用在制造时掺杂有p型杂质的p +型多晶Si膜来制造pnp晶体管的发射极。从发射电极扩散的n型杂质形成npn晶体管的n +型发射极层，而从发射极扩散的p型杂质形成pnp晶体管的p +型发射极层。因此，该方法可以产生具有更高性能的互补双极晶体管，并且适用于与用于制造亚半微米双极CMOS的工艺组合。

124. 发明授权

US5614422A Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
标题翻译：在形成第二多晶硅层之后掺杂两层双极晶体管的工艺
公开(公告)号：US5614422A
公开(公告)日：1997-03-25
申请号：US405660
申请日：1995-03-17
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L21/265
CPC分类号： H01L27/0826 , H01L21/8228 , H01L27/082
摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device. Each device is then doped with the second type impurity through the second mask. The use of the high diffusion coefficient layer in the base contact enables the base dopant to spread laterally from the edge contact to the region where the base poly is in contact with the collector, with the same diffusion cycle that is used for the emitter.
摘要翻译：减少的掩模组，用于制造（高频应用）互补双极晶体管结构的植入复杂度过程使用材料层的快速横向扩散特性，其比发射体掺杂物比单晶半导体材料高至少一个数量级。单独的基极和发射极多晶层形成为未掺杂的。然后，一个器件的发射极多晶硅和另一个器件的基极聚合物的边缘通过掺杂剂掩模曝光并同时掺杂。发射极掺杂剂直接进入发射极聚合物的表面，其位于其上并与基底接触。基极接触掺杂剂进入基极聚合物的边缘，包括具有高扩散系数的材料层，在该层上横向扩散，然后扩散到收集器材料（例如岛）表面中，以形成外部基极。图案化第二掩模以暴露第二器件的发射极和第一器件的基极poly的边缘。然后每个器件通过第二掩模掺杂第二类型杂质。在基极接触中使用高扩散系数层使得基底掺杂剂从边缘接触侧向扩散到与聚集体接触的区域，具有与用于发射极的相同的扩散循环。

125. 发明授权

US09929161B2 Complementary bipolar SRAM 有权
公开(公告)号：US09929161B2
公开(公告)日：2018-03-27
申请号：US15581646
申请日：2017-04-28
申请人： International Business Machines Corporation
发明人： Tak H. Ning
IPC分类号： H01L27/102 , G11C11/416 , G11C11/411 , H01L21/8228 , H01L21/8229
CPC分类号： G11C11/416 , G11C11/411 , G11C11/4116 , H01L21/8228 , H01L21/8229 , H01L27/1025 , H01L27/11
摘要： A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

126. 发明申请

US20170309703A1 METHOD FOR CREATING THE HIGH VOLTAGE COMPLEMENTARY BJT WITH LATERAL COLLECTOR ON BULK SUBSTRATE WITH RESURF EFFECT 审中-公开
公开(公告)号：US20170309703A1
公开(公告)日：2017-10-26
申请号：US15647493
申请日：2017-07-12
申请人： Texas Instruments Incorporated
发明人： Jeffrey A. BABCOCK , Alexei SADOVNIKOV
IPC分类号： H01L29/06 , H01L21/265 , H01L29/10 , H01L29/08 , H01L29/04 , H01L27/082 , H01L21/8228 , H01L21/762 , H01L21/308 , H01L21/306 , H01L29/16 , H01L29/732 , H01L21/266
CPC分类号： H01L29/063 , H01L21/26513 , H01L21/266 , H01L21/30604 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/8228 , H01L21/82285 , H01L27/082 , H01L27/0826 , H01L29/04 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/0826 , H01L29/1095 , H01L29/16 , H01L29/732
摘要： Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

127. 发明授权

US09653149B2 Complementary bipolar SRAM 有权
公开(公告)号：US09653149B2
公开(公告)日：2017-05-16
申请号：US14793561
申请日：2015-07-07
申请人： International Business Machines Corporation
发明人： Tak H. Ning
IPC分类号： G11C11/00 , G11C11/416 , G11C11/411 , H01L27/11 , H01L27/102
CPC分类号： G11C11/416 , G11C11/411 , G11C11/4116 , H01L21/8228 , H01L21/8229 , H01L27/1025 , H01L27/11
摘要： A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

128. 发明授权

US09536788B1 Complementary SOI lateral bipolar transistors with backplate bias 有权
标题翻译：具有背板偏置的互补SOI横向双极晶体管
公开(公告)号：US09536788B1
公开(公告)日：2017-01-03
申请号：US14886927
申请日：2015-10-19
申请人： International Business Machines Corporation
发明人： Tak H. Ning , Jeng-Bang Yau
IPC分类号： H01L21/8228 , H01L21/84 , H01L29/735 , H01L29/66 , H01L27/082 , H01L29/06 , H01L29/10 , H01L29/08
CPC分类号： H01L27/082 , H01L21/76264 , H01L21/8228 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0821 , H01L29/1008 , H01L29/66242 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/737
摘要： A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate.
摘要翻译：互补双极结型晶体管（BJT）集成结构及其制造和操作的方法。该结构包括单片基板和彼此电隔离的导电的第一和第二背板。 NPN横向BJT叠置在第一背板上，PNP横向BJT叠置在第二背板上。掩埋氧化物（BOX）层位于NPN侧面BJT和第一背板之间以及PNP侧面BJT和第二背板之间。

129. 发明申请

US20160343427A1 COMPLEMENTARY BIPOLAR SRAM 有权
标题翻译：补充双极性SRAM
公开(公告)号：US20160343427A1
公开(公告)日：2016-11-24
申请号：US14793561
申请日：2015-07-07
申请人： International Business Machines Corporation
发明人： Tak H. Ning
IPC分类号： G11C11/416
CPC分类号： G11C11/416 , G11C11/411 , G11C11/4116 , H01L21/8228 , H01L21/8229 , H01L27/1025 , H01L27/11
摘要： A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.
摘要翻译：互补横向双极型SRAM器件及其操作方法。该器件包括：第一组和第二组横向双极晶体管，形成相应的第一反相器器件和第二反相器器件，第一和第二反相器器件交叉耦合以存储逻辑状态。在每个所述第一和第二组中，第一双极晶体管是PNP型双极晶体管，第二双极晶体管是NPN型双极晶体管，每个所述NPN型双极晶体管具有基极端子，第一发射极端子，第二发射极端子和集电极端子。每个第一和第二逆变器装置的PNP型晶体管的发射极端子电耦合在一起并接收第一施加的字线电压。所述第一反相器和第二反相器装置的每个所述NPN晶体管的第一发射极端子电耦合在一起并接收第二施加电压。所述第一反相器的一个NPN双极晶体管的第二发射极端子电耦合到第一位线导体，并且所述第二反相器装置的NPN双极晶体管的第二发射极端子电耦合到第二位线。

130. 发明申请

US20160099310A1 SEMICONDUCTOR DEVICE INTEGRATING HIGH AND LOW VOLTAGE DEVICES 审中-公开
标题翻译：集成高，低电压器件的半导体器件
公开(公告)号：US20160099310A1
公开(公告)日：2016-04-07
申请号：US14968679
申请日：2015-12-14
申请人： Alpha & Omega Semiconductor Incorporated
发明人： Hideaki Tsuchiko
IPC分类号： H01L29/06 , H01L27/06
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/8222 , H01L21/8228 , H01L21/823481 , H01L21/823493 , H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/0821 , H01L27/0823 , H01L27/088 , H01L29/063 , H01L29/10 , H01L29/1079 , H01L29/1083 , H01L29/42368 , H01L29/66272 , H01L29/732 , H01L29/735 , H01L29/7816 , H01L29/7835 , H01L29/8611
摘要： The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.
摘要翻译：本发明涉及用于形成诸如双极晶体管的多个有源元件的方法。 MOSFET，二极管等，使得具有较高工作电压的有源元件可以在具有较低工作电压器件的公共衬底上形成，并结合现有的经过验证的制造较低工作电压有源元件的工艺流程。本发明还涉及一种通过在现有设备的早期制造过程中添加几个步骤来形成在相同功能的现有设备上增加操作电压的装置的方法，而不会对设备性能造成极大的影响。

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