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121. 发明授权

US06728901B1 Arithmetic built-in self-test of multiple scan-based integrated circuits 有权
标题翻译：多个基于扫描的集成电路的算术内置自检
公开(公告)号：US06728901B1
公开(公告)日：2004-04-27
申请号：US09276474
申请日：1999-03-25
申请人： Janusz Rajski , Jerzy Tyszer
发明人： Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F1300
CPC分类号： G06F11/2221 , G01R31/318385 , G01R31/318547
摘要： An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Operating logic uses data paths of the processor core to implement the ABIST. In one embodiment, operating logic generates test patterns for the peripheral devices using the data paths of the processor core, loads the test patterns into the parallel scan registers of the peripheral devices, recovers test responses from the parallel scan registers, and compacts responses from the peripheral devices once again using the data paths of the processor core.
摘要翻译：一种装置和方法提供了具有耦合到处理器核心的并行扫描寄存器的多个外围设备的算术内置自检（ABIST），全部在集成电路内。操作逻辑使用处理器内核的数据路径实现ABIST。在一个实施例中，操作逻辑使用处理器核心的数据路径为外围设备生成测试模式，将测试模式加载到外围设备的并行扫描寄存器，恢复来自并行扫描寄存器的测试响应，并压缩来自外围设备再次使用处理器核心的数据路径。

122. 发明授权

US06557129B1 Method and apparatus for selectively compacting test responses 有权
公开(公告)号：US06557129B1
公开(公告)日：2003-04-29
申请号：US09619988
申请日：2000-07-20
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

123. 发明授权

US06539409B2 Method for synthesizing linear finite state machines 有权
公开(公告)号：US06539409B2
公开(公告)日：2003-03-25
申请号：US09957701
申请日：2001-09-18
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G06F102
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

124. 发明授权

US5737340A Multi-phase test point insertion for built-in self test of integrated circuits 失效
标题翻译：集成电路内置自检的多相测试点插入
公开(公告)号：US5737340A
公开(公告)日：1998-04-07
申请号：US678376
申请日：1996-07-01
申请人： Nagesh Tamarapalli , Janusz Rajski
发明人： Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/318342 , G06F17/5022 , G06F2217/14
摘要： Method and apparatus for providing high quality Built-in-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.
摘要翻译：提供集成电路高质量内置自检（BIST）的方法和设备，同时保证了测试模式下的融合，减少了面积开销和功耗。分割和征服方法用于将测试分成多个阶段，在此阶段将多个测试模式应用于被测电路（CUT）。每个阶段的设计（控制和观测点的选择）都是逐渐减少的未检测到的故障列表。在一个阶段中，使用独特的概率故障模拟（PFS）技术来识别到目前为止所达到的最大限度地有助于故障覆盖的一组控制点。 PFS技术准确地计算电路的传播特性，并使用它来确定在目前为止选择的控制点存在时新控制点的影响。以这种方式，在每个新阶段，启用由固定值驱动并且协同操作的一组控制点。以类似的方式选择观测点，以进一步增强故障覆盖。然后将控制和观测点的集合插入到被测电路中，并通过精确的故障模拟确定未被检测的故障的新的减少的列表。该过程是迭代的，并且持续到未检测到的故障的数量小于或等于可接受的阈值，已经插入了预定数量的控制和观察点，或者达到了指定的测试阶段的最大数目。

125. 发明授权

US08832512B2 Low power compression of incompatible test cubes 有权
标题翻译：不兼容的测试立方体的低功率压缩
公开(公告)号：US08832512B2
公开(公告)日：2014-09-09
申请号：US13049829
申请日：2011-03-16
申请人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

126. 发明授权

US08533547B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
公开(公告)号：US08533547B2
公开(公告)日：2013-09-10
申请号：US13013712
申请日：2011-01-25
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

127. 发明授权

US08499209B2 At-speed scan testing with controlled switching activity 有权
标题翻译：具有受控切换活动的高速扫描测试
公开(公告)号：US08499209B2
公开(公告)日：2013-07-30
申请号：US12765530
申请日：2010-04-22
申请人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
发明人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
IPC分类号： G01R31/28 , G06F11/00 , G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G01R31/318547 , G01R31/318575
摘要： Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
摘要翻译：通过用功能背景数据填充测试立方体的未指定位来生成速度扫描测试的测试模式。功能背景数据是当被测电路的开关活动接近稳定状态时观察到的扫描单元值。还公布了EDT（嵌入式确定性测试）环境中的硬件实现。

128. 发明申请

US20110320999A1 DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS 有权
标题翻译：用于测试模式的低功率分解的分解器
公开(公告)号：US20110320999A1
公开(公告)日：2011-12-29
申请号：US13225240
申请日：2011-09-02
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

129. 发明申请

US20110231721A1 LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES 有权
标题翻译：低功耗压缩不完全测试
公开(公告)号：US20110231721A1
公开(公告)日：2011-09-22
申请号：US13049829
申请日：2011-03-16
申请人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00 , G06F1/32
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

130. 发明申请

US20110055646A1 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT 审中-公开
标题翻译：记忆环境中的故障诊断
公开(公告)号：US20110055646A1
公开(公告)日：2011-03-03
申请号：US12678747
申请日：2008-09-18
申请人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.
摘要翻译：公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在多个时间相关存储器的检测中进行存储器内置自检操作的能力测试失败。在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自在内存测试的测试步骤中的嵌入式存储器阵列。在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

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