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121. 发明授权

US06281589B1 System of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides 有权
标题翻译：选择性地清洗铜基板表面的系统，原位去除铜氧化物
公开(公告)号：US06281589B1
公开(公告)日：2001-08-28
申请号：US09270901
申请日：1999-03-15
申请人： Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
发明人： Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21302
CPC分类号： C23G5/00 , H01L21/02063 , H01L21/02068 , H01L21/31111 , H01L21/31138 , H01L21/32134 , H01L21/76838
摘要： A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with &bgr;-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed. An IC having a metal interconnection, in which the underlying copper layer is cleaned of copper oxides, in-situ with Hhfac vapor, is also provided.
摘要翻译：提供了一种选择性地蚀刻不含铜氧化物的铜表面以准备沉积互连金属材料的系统和方法。该方法用β-二酮除去金属氧化物，如Hhfac。 Hhfac以蒸气形式输送到系统中，几乎完全与铜氧化物反应。清洁过程的副产物同样是挥发性的，用于在真空压力下从系统中除去。由于该方法很容易适用于大多数IC工艺系统，所以它可以在无氧环境中进行，而不会从处理室中移除IC。在沉积互连金属之前，原位清洁工艺允许最小量的氧化铜重整。以这种方式，形成铜表面和互连金属材料之间的高导电性电互连。还提供了具有金属互连的IC，其中下面的铜层用Hhfac蒸气原位清除了铜氧化物。

122. 发明授权

US06242771B1 Chemical vapor deposition of PB5GE3O11 thin film for ferroelectric applications 失效
标题翻译：用于铁电应用的PB5GE3O11薄膜的化学气相沉积
公开(公告)号：US06242771B1
公开(公告)日：2001-06-05
申请号：US09291688
申请日：1999-04-13
申请人： Sheng Teng Hsu , Chien Hsiung Peng , Jong Jan Lee
发明人： Sheng Teng Hsu , Chien Hsiung Peng , Jong Jan Lee
IPC分类号： H01L29788
CPC分类号： H01L28/55 , C23C16/40 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/78391
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.
摘要翻译：在单晶硅的衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括：形成用于FEM门单元的硅器件区域; 处理器件区域以形成源极，栅极和漏极区域; 在所述栅极结区域上沉积FEM栅极单元，包括沉积下电极，通过化学气相沉积（CVD）沉积c轴取向的Pb5Ge3O11FE层，以及沉积上电极; 以及围绕所述FEM门单元沉积绝缘结构。铁电存储器（FEM）单元包括：单晶硅衬底，其包括其中具有源极，栅极和漏极区域的有源区; 包括下电极，由CVD形成的c轴取向Pb5Ge3O11FE层和上电极的有限元门单元; 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，栅极和漏极。

123. 发明授权

US06184157B2 Stress-loaded film and method for same 失效
标题翻译：应力负荷膜及其方法
公开(公告)号：US06184157B2
公开(公告)日：2001-02-06
申请号：US09088456
申请日：1998-06-01
申请人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
发明人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
IPC分类号： B05D306
CPC分类号： C23C14/50 , C23C14/06 , C23C14/22 , C23C16/30 , C23C16/44 , C23C16/4582
摘要： A method has been provided to counteract the inherent tension in a deposited film. A wafer substrate is fixed to a wafer chuck having a curved surface. When the chuck surface is convex, a tensile stress is implanted in a deposited film. Upon release from the chuck, the deposited film develops a compressive stress. When the chuck surface is concave, a compressive stress is implanted in the deposited film. Upon release from the chuck, the deposited film develops a tensile stress. Loading a film with a compressive stress is helpful in making films having an inherently tensile stress become thermal stable. Stress loading is also used to improve adhesion between films, and to prevent warping of a film during annealing. A product-by-process using the above-described method is also provided.
摘要翻译：已经提供了一种抵消沉积膜中的固有张力的方法。将晶片基板固定到具有弯曲表面的晶片卡盘。当卡盘表面凸出时，在沉积膜中注入拉伸应力。当从卡盘释放时，沉积的膜产生压缩应力。当卡盘表面凹陷时，在沉积膜中注入压应力。当从卡盘释放时，沉积的膜产生拉伸应力。加载具有压应力的薄膜有助于使具有固有拉伸应力的薄膜变得热稳定。应力负荷也用于提高膜之间的粘附性，并且防止退火期间膜的翘曲。还提供了使用上述方法的逐个方法。

124. 发明授权

US6117691A Method of making a single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization 有权
标题翻译：制造具有不对称铁电极化的单晶体管铁电存储单元的方法
公开(公告)号：US6117691A
公开(公告)日：2000-09-12
申请号：US287726
申请日：1999-04-07
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01G7/06
CPC分类号： H01L21/84 , G11C11/22 , H01L21/28291 , H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of the first type in the conductive channel well of the second type to form a conductive channel of the first conductivity type for use as a gate junction region, implanting doping impurities of the second type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of the second conductivity type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region.A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of the first conductive type formed in the second conductivity type well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of second conductive type. A FEM gate unit overlays the conductive channel of the gate junction region. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.
摘要翻译：在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到所述第一类型的导电通道形成第二类型的导电通道阱，在所述第二类型的导电通道阱中注入所述第一类型的掺杂杂质，以形成用作栅极结区域的第一导电类型的导电沟道在栅极结区域的任一侧将第二类型的导电沟道子阱中的第二类型的掺杂杂质注入，以形成用作源极结区域和漏极结区域的第二导电类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在第二导电类型阱结构中的第一导电类型的结构，用作栅极结区域。源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂形成第二导电类型的导电沟道。有限元栅极单元覆盖栅极结区域的导电沟道。绝缘层覆盖了连接区域，FEM栅极单元和衬底。合适的电极连接到存储单元中的各种有源区。

125. 发明授权

US6048738A Method of making ferroelectric memory cell for VLSI RAM array 失效
标题翻译：制造VLSI RAM阵列的铁电存储单元的方法
公开(公告)号：US6048738A
公开(公告)日：2000-04-11
申请号：US870375
申请日：1997-06-06
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： G11C11/22 , H01L21/28 , H01L21/8246 , H01L21/84 , H01L27/115 , H01L29/78 , H01G7/06
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/78391 , G11C11/223
摘要： A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of said gate region, a MOS capacitor, a FEM capacitor, wherein said FEM capacitor is stacked on and overlays at least a portion of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit.
摘要翻译：在硅衬底上形成半导体存储器件的方法包括在硅衬底中注入第一类型的掺杂杂质以形成用作栅极结区域的第一类型的导电沟道，在导电沟道上形成MOS电容器第一类型，在MOS电容器上沉积FEM电容器，从而形成堆叠栅极单元，在栅极结区域的任一侧上在硅衬底中注入第二类型的掺杂杂质以形成第二类型的导电沟道用于作为源极结区域和漏极结区域，以及围绕FEM栅极单元沉积绝缘结构。根据本发明构造的铁电存储器（FEM）单元包括硅衬底，位于所述衬底中的栅极区，位于所述栅极区两侧的源极结区域和漏极结区域，MOS电容器，FEM电容器，其中所述FEM电容器堆叠在所述MOS电容器的至少一部分上并覆盖所述MOS电容器，从而与所述MOS电容器形成堆叠栅极单元。

126. 发明授权

US5904565A Low resistance contact between integrated circuit metal levels and method for same 失效
标题翻译：集成电路金属级之间的低电阻接触和相同的方法
公开(公告)号：US5904565A
公开(公告)日：1999-05-18
申请号：US896114
申请日：1997-07-17
申请人： Tue Nguyen , Sheng Teng Hsu
发明人： Tue Nguyen , Sheng Teng Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L21/76865 , H01L23/5226 , H01L21/28568 , H01L21/76838 , H01L2924/0002 , H01L2924/3011
摘要： A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.
摘要翻译：公开了一种在IC中形成直接铜铜铜连接电平的方法。通过互连形成通过绝缘体将通孔绝缘体上的阻挡材料各向同性地沉积到较低的铜电平，然后各向异性地蚀刻通孔以除去覆盖较低铜层的阻挡材料。各向异性蚀刻离开通过绝缘体衬套通孔的阻挡材料。随后沉积的上层金属层，当通孔填充时，直接接触下铜层。通过蚀刻绝缘体中的互连沟槽并且在沟槽底部中各向异性地沉积非导电阻挡材料来形成双镶嵌互连。然后，通孔从沟槽互连形成为较低的铜层。如上所述，导电阻挡材料在沟槽/通孔结构中各向同性地沉积，并进行各向异性蚀刻以去除覆盖较低铜层的阻挡材料。绝缘阻隔材料，衬在沟槽和通孔，仍然存在。还提供了根据上述方法制造的通过互连结构和双镶嵌互连结构的IC。

127. 发明授权

US5891782A Method for fabricating an asymmetric channel doped MOS structure 失效
标题翻译：制造不对称沟道掺杂MOS结构的方法
公开(公告)号：US5891782A
公开(公告)日：1999-04-06
申请号：US918678
申请日：1997-08-21
申请人： Sheng Teng Hsu , Jong Jan Lee
发明人： Sheng Teng Hsu , Jong Jan Lee
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L21/8234
CPC分类号： H01L29/78624 , H01L29/66772 , H01L29/78696
摘要： A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
摘要翻译：提供了一种形成在沟道区和漏极之间没有轻掺杂漏极（LDD）区的MOS晶体管的方法。沟道区域是在淀积栅极氧化物层之后由倾斜的离子注入形成的。相对于栅电极的长度，倾斜注入形成相对短的沟道长度。通道的位置偏移，并直接与源相邻。在漏极附近的栅极下方的非沟道区域替代通道和漏极之间的LDD区域。这种漏极扩展用于更均匀地分布电场，使得可以实现大的击穿电压。较小的通道长度和消除与源极相邻的LDD区域起到降低源极和漏极之间的电阻的作用。以这种方式，获得更大的Id电流和更快的开关速度。还提供了具有短的偏置沟道和漏极延伸的MOS晶体管。

128. 发明授权

US07968419B2 Back-to-back metal/semiconductor/metal (MSM) Schottky diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US07968419B2
公开(公告)日：2011-06-28
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

129. 发明授权

US07727897B2 Method of etching a TE/PCMO stack using an etch stop layer 有权
标题翻译：使用蚀刻停止层蚀刻TE / PCMO堆叠的方法
公开(公告)号：US07727897B2
公开(公告)日：2010-06-01
申请号：US11215519
申请日：2005-08-30
申请人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
发明人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L28/55 , H01L21/31122
摘要： A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.
摘要翻译：使用蚀刻停止层蚀刻顶部电极/铁电体堆叠的方法包括在衬底上形成第一电介质材料的第一层; 在第一介电材料的第一层中形成底电极; 在所述第一电介质材料和所述底电极的所述第一层上沉积蚀刻停止层，包括在其中形成孔; 沉积一层铁电材料层并在铁电材料上沉积顶部电极材料以形成顶部电极/铁电堆叠; 堆叠蚀刻顶部电极和铁电材料; 沉积封装上电极和铁电材料的第二电介质材料层; 蚀刻第二介电材料的层以形成围绕顶电极和铁电材料的侧壁; 以及沉积所述第一介电材料的第二和第三层。

130. 发明授权

US07675056B2 Germanium phototransistor with floating body 有权
标题翻译：具有浮体的锗光电晶体管
公开(公告)号：US07675056B2
公开(公告)日：2010-03-09
申请号：US11891574
申请日：2007-08-10
申请人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
发明人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

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