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121. 发明授权

US07420119B2 Subterranean electrical hub 失效
标题翻译：地下电气枢纽
公开(公告)号：US07420119B2
公开(公告)日：2008-09-02
申请号：US11564337
申请日：2006-11-29
申请人： Joseph John Janos , John Joseph Ascherl , Michael William Briggs , Raymond J. Fritz , Richard Williams
发明人： Joseph John Janos , John Joseph Ascherl , Michael William Briggs , Raymond J. Fritz , Richard Williams
IPC分类号： H01H9/02
CPC分类号： H01R25/003 , H01R13/52 , H01R13/625 , H01R13/71 , H01R25/00
摘要： An exemplary subterranean hub for an outdoor system for distributing electrical power to a plurality of fixtures is provided, the hub having a body, a plurality of electrical connectors disposed on the body and adapted to accept mating connectors from a corresponding fixtures, means for electrically coupling an external power source to the electrical connectors, and a depth reference marker, connected to the body and adapted to provide a visual verification that the hub is buried at a sufficient depth during installation of the hub.
摘要翻译：提供了一种用于将电力分配给多个固定装置的室外系统的示例性地下轮毂，所述轮毂具有主体，设置在所述主体上的多个电连接器，并且适于接收来自相应固定装置的配合连接器，用于电耦合的装置电连接器的外部电源和深度参考标记，其连接到主体并且适于在轮毂的安装期间提供轮毂被埋在足够的深度的视觉验证。

122. 发明申请

US20080156449A1 Paper articles exhibiting water resistance and method for making same 有权
标题翻译：具有耐水性的纸制品及其制造方法
公开(公告)号：US20080156449A1
公开(公告)日：2008-07-03
申请号：US11904611
申请日：2007-09-27
申请人： Richard Williams , Peter M. Froass , Sandeep Kulkarni
发明人： Richard Williams , Peter M. Froass , Sandeep Kulkarni
IPC分类号： D21H17/34 , D21H17/28 , D21H17/37 , D21H17/57
CPC分类号： D21H23/26 , D21H17/72 , D21H21/16 , D21H21/54 , Y10T428/25 , Y10T428/31591 , Y10T428/31808 , Y10T428/31848 , Y10T428/31895 , Y10T428/31902 , Y10T428/31906 , Y10T428/31964 , Y10T428/31975 , Y10T428/31993
摘要： This invention relates to a process for preparing sized paper and paperboard which incorporates in the paper and paperboard at the size press size a composition comprising one or more “hydrophobic polymers” wherein hydrophobic polymers, the amount of such polymers and the weight ratio of starch to such polymer in the composition are selected such that the paper and paper board exhibits a Cobb Value equal to or less than about 25 and to a sized paper or paperboard web formed by the process.
摘要翻译：本发明涉及一种用于制备尺寸纸和纸板的方法，其中以压片尺寸将纸和纸板结合在一起，该组合物包含一种或多种“疏水性聚合物”，其中疏水聚合物，这种聚合物的量以及淀粉与选择组合物中的这种聚合物，使得纸和纸板显示等于或小于约25的Cobb值以及通过该方法形成的尺寸的纸或纸板纤维网。

123. 发明申请

US20080105900A1 FET Channel Having a Strained Lattice Structure Along Multiple Surfaces 审中-公开
标题翻译：具有沿多个表面的应变晶格结构的FET通道
公开(公告)号：US20080105900A1
公开(公告)日：2008-05-08
申请号：US11970011
申请日：2008-01-07
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

124. 发明申请

US20080093227A1 Error detection in analyte measurements based on measurement of system resistance 有权
标题翻译：基于测量系统电阻的分析物测量中的误差检测
公开(公告)号：US20080093227A1
公开(公告)日：2008-04-24
申请号：US11874766
申请日：2007-10-18
申请人： Steven Diamond , Ian Harding , Richard Williams
发明人： Steven Diamond , Ian Harding , Richard Williams
IPC分类号： G01N27/26 , G01N27/28
CPC分类号： G01N27/3274
摘要： Measurement of the series track resistance of a working and counter electrode pair in an electrochemical test strip provide error detection for multiple variations in the quality of the test strip, as well as the operation of strip in the test meter. In particular, a single measurement of series resistance can be used to detect and generate an error message when an incorrect reading is likely to result due to (1) damaged electrode tracks, (2) fouled electrode surfaces, (3) dirty strip contacts, or (4) short circuit between the electrodes.
摘要翻译：在电化学测试条中测量工作电极对和对电极对的串联轨道电阻可以提供测试条质量的多种变化的错误检测以及测试仪中条带的操作。特别地，当由于（1）损坏的电极轨迹，（2）污染的电极表面，（3）脏的带状接触，或者（3））导致不正确的读数时，可以使用串联电阻的单次测量来检测并产生错误信息，或（4）电极之间的短路。

125. 发明申请

US20080061367A1 High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same 有权
公开(公告)号：US20080061367A1
公开(公告)日：2008-03-13
申请号：US11982780
申请日：2007-11-05
申请人： Richard Williams , Donald Disney
发明人： Richard Williams , Donald Disney
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

126. 发明申请

US20080039581A1 Triarylamine Compounds, Compositions and Devices 审中-公开
标题翻译：三芳胺化合物，组合物和装置
公开(公告)号：US20080039581A1
公开(公告)日：2008-02-14
申请号：US11572872
申请日：2005-07-21
申请人： Beverley Anne Brown , Stephen William Leeming , Richard Williams
发明人： Beverley Anne Brown , Stephen William Leeming , Richard Williams
IPC分类号： C07C211/00 , C08F2/10
CPC分类号： C07C211/54
摘要： The invention relates to a compound of Formula (I): wherein: each of R1, R2, R3, R4, R5, R6 and R7 which may be the same or different on each triarylamine unit of Formula (1) and the same or different from one triarylamine unit of Formula (1) to another is independently hydrogen or an optionally substituted substituent; n is from 5 to 20; and a and b are each independently 0, 1, 2, 3 or 4. Also claimed are compositions comprising a compound of Formula (1) and a synthetic organic polymer resin, a process for preparing a compound of Formula (1), an organic semiconducting layer prepared from the composition, and electronic devices comprising the organic semiconducting layer.
摘要翻译：本发明涉及式（I）的化合物：其中：R 1，R 2，R 3，R 3， R 5，R 5，R 6和R 7可以在式（1）的每个三芳基胺单元上相同或不同）并且与式（1）的一个三芳基胺单元相同或不同，独立地为氢或任选取代的取代基; n为5〜20; 和a和b各自独立地为0,1,2,3或4.还要求保护的是包含式（1）的化合物和合成的有机聚合物树脂的组合物，制备式（1）化合物的方法，有机由该组合物制备的半导体层以及包含有机半导体层的电子器件。

127. 发明申请

US20080007192A1 Temperature-dependent power adjustment of transmitter 有权
标题翻译：变送器温度依赖功率调节
公开(公告)号：US20080007192A1
公开(公告)日：2008-01-10
申请号：US11479184
申请日：2006-06-29
申请人： Richard Williams , Pauli Heikkinen , Jeff Brownlee , Debbie Richardson , Ilkka Savimaki , Gairn Kalla
发明人： Richard Williams , Pauli Heikkinen , Jeff Brownlee , Debbie Richardson , Ilkka Savimaki , Gairn Kalla
IPC分类号： H02H7/08
CPC分类号： H03G3/3042 , H03G3/3047 , H04B1/036
摘要： A device includes a transmitter, at least one temperature sensor; and a controller. The controller is responsive to the at least one temperature sensor indicating that a temperature has risen above a first threshold to control the transmitter to reduce transmit power from a first power level to a second power level, wherein the second power level is a non-zero power level.
摘要翻译：一种装置包括一个发射器，至少一个温度传感器; 和控制器。所述控制器响应于所述至少一个温度传感器，其指示温度已升至高于第一阈值，以控制所述发射器将发射功率从第一功率电平降低到第二功率电平，其中所述第二功率电平为非零能量等级。

128. 发明申请

US20070272986A1 Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology 有权
公开(公告)号：US20070272986A1
公开(公告)日：2007-11-29
申请号：US11881841
申请日：2007-07-30
申请人： Richard Williams , Michael Cornell , Wai Chen
发明人： Richard Williams , Michael Cornell , Wai Chen
IPC分类号： H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

129. 发明申请

US20070134851A1 Space-efficient package for laterally conducting device 有权
公开(公告)号：US20070134851A1
公开(公告)日：2007-06-14
申请号：US11701761
申请日：2007-02-02
申请人： James Harnden , Allen Lam , Richard Williams , Anthony Chia , Chu Weibing
发明人： James Harnden , Allen Lam , Richard Williams , Anthony Chia , Chu Weibing
IPC分类号： H01L21/00
CPC分类号： H01L23/49562 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/014 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

130. 发明申请

US20070131938A1 Merged and Isolated Power MESFET Devices 审中-公开
标题翻译：合并和隔离电源MESFET器件
公开(公告)号：US20070131938A1
公开(公告)日：2007-06-14
申请号：US11307204
申请日：2006-01-26
申请人： Richard Williams
发明人： Richard Williams
IPC分类号： H01L31/0312 , H01L29/76
CPC分类号： H01L27/0605 , H01L27/085
摘要： A first type of merged power MESFET device includes two monolithically integrated MESFETS. The MESFETS share common sources and gates, and are sized so that one MESFET may be used as a power device while the other is used as a current-sense device. A second type of merged power MESFET device includes two monolithically integrated MESFETS. The MESFETS share a common region which serves as the source for one MESFET and the drain for the second MESFET. This allows the two MESFETS to function as the high and low-side switches for a buck or boost regulator. A third type of merged power MESFET device combines the high and low-side switches with a current-sensing device.
摘要翻译：第一种合并功率MESFET器件包括两个单片集成的MESFETS。 MESFETS共享共同的源极和栅极，其尺寸使得一个MESFET可以用作功率器件，而另一个用作电流检测器件。第二种合并功率MESFET器件包括两个单片集成的MESFETS。 MESFETS共享一个公共区域，其作为一个MESFET的源极和第二个MESFET的漏极。这允许两个MESFETS用作降压或升压稳压器的高侧和低侧开关。第三种合并功率MESFET器件将高端和低端开关与电流检测器件相结合。

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