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121. 发明授权

US07763943B2 Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
标题翻译：通过结合部分金属翅片来减少多栅极器件的外部电阻
公开(公告)号：US07763943B2
公开(公告)日：2010-07-27
申请号：US11964623
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/785 , H01L29/66795
摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
摘要翻译：通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体部分联接在一起。

122. 发明授权

US07745270B2 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US07745270B2
公开(公告)日：2010-06-29
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/84
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上形成多晶硅层并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

123. 发明授权

US07727830B2 Fabrication of germanium nanowire transistors 有权
标题翻译：锗纳米线晶体管的制造
公开(公告)号：US07727830B2
公开(公告)日：2010-06-01
申请号：US12006273
申请日：2007-12-31
申请人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
发明人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
IPC分类号： H01L21/337
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译：通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

124. 发明授权

US07545003B2 Defect-free source/drain extensions for MOSFETS having germanium based channel regions 有权
标题翻译：具有锗基通道区域的MOSFET的无缺陷源极/漏极扩展
公开(公告)号：US07545003B2
公开(公告)日：2009-06-09
申请号：US11864907
申请日：2007-09-29
申请人： Prashant Majhi , William Tsai , Jack T. Kavalieros
发明人： Prashant Majhi , William Tsai , Jack T. Kavalieros
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/7833
摘要： A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.
摘要翻译：用于形成用于基于锗基通道区域的MOSFET的无缺陷源极和漏极延伸的工艺在半导体衬底上沉积第一硅锗层，在硅锗层上沉积栅极电介质层，并将栅极电极层沉积在栅介质层。干蚀刻化学蚀刻这些层以在半导体衬底上形成栅电极，栅极电介质和硅锗沟道区。接下来，离子注入工艺形成消耗硅锗沟道区和半导体衬底的部分的卤素注入区。最后，原位掺杂外延沉积工艺生长了一对具有LDD区的硅锗层。硅锗层与硅锗沟道区相邻，并且卤素注入区不会损坏硅锗层的任何部分。

125. 发明申请

US20090127541A1 REDUCING DEFECTS IN SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURES 审中-公开
标题翻译：减少半导体器件中的缺陷量子阱结构
公开(公告)号：US20090127541A1
公开(公告)日：2009-05-21
申请号：US11942312
申请日：2007-11-19
申请人： Prashant Majhi , Wilman Tsai , Jack T. Kavalieros
发明人： Prashant Majhi , Wilman Tsai , Jack T. Kavalieros
IPC分类号： H01L21/205 , H01L29/12
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/66477 , H01L29/78
摘要： Reducing defects in semiconductor quantum well structures is generally described. In one example, an apparatus includes a semiconductor substrate including silicon, a buffer film epitaxially grown on the semiconductor substrate, the buffer film comprising silicon, germanium, and an impurity, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film and wherein the impurity disrupts lattice structure dislocation gliding in at least the first semiconductor film.
摘要翻译：通常描述半导体量子阱结构中的减少缺陷。在一个示例中，一种装置包括：半导体衬底，包括硅，外延生长在半导体衬底上的缓冲膜，包括硅，锗和杂质的缓冲膜;以及在缓冲膜上外延生长的第一半导体膜，其中晶格失配存在于半导体衬底和第一半导体膜之间，并且其中杂质破坏至少第一半导体膜中的晶格结构位错滑动。

126. 发明申请

US20090039476A1 Apparatus and method for selectively recessing spacers on multi-gate devices 审中-公开
标题翻译：用于在多栅极器件上选择性地凹入间隔物的装置和方法
公开(公告)号：US20090039476A1
公开(公告)日：2009-02-12
申请号：US12287319
申请日：2008-10-07
申请人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
发明人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
IPC分类号： H01L21/311 , H01L21/306 , H01L29/51
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66795 , H01L29/785 , Y10S257/90
摘要： Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于在多栅极晶体管的一部分上制造间隔物而不在多栅极晶体管的另一部分上形成间隔物的方法的实施例。可以描述和要求保护其他实施例。

127. 发明申请

US20080038924A1 Highly-selective metal etchants 失效
标题翻译：高选择性金属蚀刻剂
公开(公告)号：US20080038924A1
公开(公告)日：2008-02-14
申请号：US11501379
申请日：2006-08-08
申请人： Willy Rachmady , Jack T. Kavalieros , Mark Y. Liu , Mark L. Doczy
发明人： Willy Rachmady , Jack T. Kavalieros , Mark Y. Liu , Mark L. Doczy
IPC分类号： H01L21/302
CPC分类号： H01L21/32134 , C23F1/02 , H01L29/66545
摘要： A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one embodiment, the wet etchant is utilized to pattern a metal layer in a semiconductor structure. In another embodiment, a highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is used to pattern a metal gate electrode in a replacement gate processing scheme.
摘要翻译：描述了具有包含一种或多种类型的具有两个或更多个氧原子的分子的活性成分的高选择性金属湿蚀刻剂。在一个实施例中，使用湿蚀刻剂来图案化半导体结构中的金属层。在另一个实施方案中，使用具有包含一种或多种类型的具有两个或更多个氧原子的分子的活性成分的高度选择性金属湿蚀刻剂以在替换栅极处理方案中对金属栅极电极进行图案化。

128. 发明授权

US07316949B2 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US07316949B2
公开(公告)日：2008-01-08
申请号：US11248737
申请日：2005-10-11
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

129. 发明申请

US20070287255A1 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US20070287255A1
公开(公告)日：2007-12-13
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

130. 发明申请

US20230090092A1 CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION METAL 有权
公开(公告)号：US20230090092A1
公开(公告)日：2023-03-23
申请号：US17448382
申请日：2021-09-22
申请人： Aaron D. Lilak , Orb Acton , Cheng-Ying Huang , Gilbert Dewey , Ehren Mannebach , Anh Phan , Willy Rachmady , Jack T. Kavalieros
发明人： Aaron D. Lilak , Orb Acton , Cheng-Ying Huang , Gilbert Dewey , Ehren Mannebach , Anh Phan , Willy Rachmady , Jack T. Kavalieros
IPC分类号： H01L27/12 , H01L21/84
摘要： An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

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