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121. 发明申请

US20130256763A1 LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION 有权
标题翻译： SRAM扩展中的低延伸剂量植入
公开(公告)号：US20130256763A1
公开(公告)日：2013-10-03
申请号：US13464267
申请日：2012-05-04
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.
摘要翻译：静态随机存取存储器制造阵列包括至少一个p型场效应晶体管，其包括栅极堆叠和形成具有栅极长度L gate和有效栅极长度的栅极的隔离间隔，Leff以及与栅极堆叠相邻的源极和漏极区域其中源极和漏极区域由低延伸剂量植入物形成，其降低了Lgate和Leff之间的差异。

122. 发明授权

US08531871B2 8-transistor SRAM cell design with Schottky diodes 有权
标题翻译：具有肖特基二极管的8晶体管SRAM单元设计
公开(公告)号：US08531871B2
公开(公告)日：2013-09-10
申请号：US13345619
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/00 , G11C11/417
CPC分类号： G11C11/417 , G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
摘要翻译：一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

123. 发明授权

US08502325B2 Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance 有权
标题翻译：具有用于降低寄生电容的硅侧壁的金属高K晶体管
公开(公告)号：US08502325B2
公开(公告)日：2013-08-06
申请号：US13432395
申请日：2012-03-28
申请人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
发明人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
IPC分类号： H01L21/70 , H01L27/12 , H01L21/02 , H01L29/78 , H01L21/338 , H01L21/8238 , H01L21/336 , H01L21/76 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823864 , H01L21/26586 , H01L21/28105 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.
摘要翻译：一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层，选择性地去除仅第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

124. 发明申请

US20130176770A1 8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES 有权
标题翻译：具有内部通孔结型二极管的8位晶体管SRAM单元设计
公开(公告)号：US20130176770A1
公开(公告)日：2013-07-11
申请号：US13345629
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到写入位线的每个通过栅极晶体管的源极或漏极; 导通栅极和下拉晶体管的共用源极/漏极端子处的内部结二极管，用于阻止从写位线到电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

125. 发明授权

US08397183B2 Generation of asymmetric circuit devices 有权
标题翻译：生成不对称电路器件
公开(公告)号：US08397183B2
公开(公告)日：2013-03-12
申请号：US12699621
申请日：2010-02-03
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于创建适当的块级形状以制造不对称场效应晶体管（FET）。在一个实施例中，该方法包括获得具有有源区域电平（RX）和栅极区域电平（PC）的集成电路设计，RX和PC电平中的每一个具有表示半导体区域的多个形状; 并且从RX和PC级形状定义具有多个SD级形状的新级别SD。该方法还包括确定哪些新形状是源区，哪些是形成漏区; 确定哪个源区域正在向上，哪些指向下？并复制向上指向的源区域的形状和指向下一个额定的定义的级别的源区域的形状。

126. 发明申请

US20120317062A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20120317062A1
公开(公告)日：2012-12-13
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

127. 发明申请

US20120313174A1 METHOD OF MAKING A MOSFET HAVING SELF-ALIGNED SILICIDED SCHOTTKY BODY TIE INCLUDING INTENTIONAL PULL-DOWN OF AN STI EXPOSING SIDEWALLS OF A DIFFUSION REGION 审中-公开
标题翻译：制造具有自对准硅酸钙肖特基体的MOSFET的方法，包括暴露在扩散区域的边缘的潜在的下拉
公开(公告)号：US20120313174A1
公开(公告)日：2012-12-13
申请号：US13590324
申请日：2012-08-21
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A self-aligned transistor device includes: a source region and drain regions disposed on an oxide layer; a channel with a diffusion region formed between the drain and source regions; a silicide layer over a top surface of the source and drain regions, extending into the diffusion region; and a recess formed on each end of the device to expose sidewalls of the device to a free surface by performing shallow trench isolation on the oxide layer of the device that extends past the silicide layer.
摘要翻译：自对准晶体管器件包括：设置在氧化物层上的源极区域和漏极区域; 在漏极和源极区域之间形成有扩散区域的沟道; 在源极和漏极区域的顶表面上方的硅化物层，延伸到扩散区域中; 以及通过在延伸穿过硅化物层的器件的氧化物层上进行浅沟槽隔离，形成在器件的每个端部上的凹部以将器件的侧壁暴露于自由表面。

128. 发明授权

US08261138B2 Test structure for characterizing multi-port static random access memory and register file arrays 有权
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件阵列的测试结构
公开(公告)号：US08261138B2
公开(公告)日：2012-09-04
申请号：US11552158
申请日：2006-10-24
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

129. 发明授权

US08247877B2 Structure with reduced fringe capacitance 有权
标题翻译：具有降低的边缘电容的结构
公开(公告)号：US08247877B2
公开(公告)日：2012-08-21
申请号：US12550543
申请日：2009-08-31
申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey Sleight
发明人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L21/28247 , H01L29/495 , H01L29/4966
摘要： A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.
摘要翻译：一种结构包括衬底和设置在衬底上的栅叠层。该结构还包括设置在栅极堆叠的侧壁上并已经暴露于等离子体源的氮化物封装层。该结构还包括在氮化物封装层接触栅叠层的侧壁的区域中与氮化物封装层接触的至少一个其它元件。

130. 发明申请

US20120171819A1 ADAPTIVE INTERCONNECT STRUCTURE 有权
标题翻译：自适应互连结构
公开(公告)号：US20120171819A1
公开(公告)日：2012-07-05
申请号：US13417444
申请日：2012-03-12
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L21/50
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

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