专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明授权

US5913189A Voice compression system having robust in-band tone signaling and related method 失效
标题翻译：语音压缩系统具有鲁棒的带内信令和相关方法
公开(公告)号：US5913189A
公开(公告)日：1999-06-15
申请号：US798690
申请日：1997-02-12
申请人： Ho Lee , Jeanne Hall , Dan Housam
发明人： Ho Lee , Jeanne Hall , Dan Housam
IPC分类号： G10L19/00 , G10L3/00 , H04L15/00
CPC分类号： G10L19/00
摘要： A communication system, and related method, for reliably transmitting DTMF code signals through a low-bit rate channel employing a VSELP speech compression algorithm. The system adds relatively low-level noise to the analog DTMF signals before encoding by the compression algorithm. By adding the low-level noise to the DTMF signals, the tones associated with the DTMF signals can be reliably detected on the receiving end.
摘要翻译：一种用于通过采用VSELP语音压缩算法的低比特率信道可靠地发送DTMF码信号的通信系统及相关方法。该系统在通过压缩算法进行编码之前，将模拟DTMF信号增加相对较低的噪声。通过将低电平噪声添加到DTMF信号，可以在接收端可靠地检测到与DTMF信号相关联的音调。

122. 发明授权

US5633982A Removal of swirl artifacts from celp-based speech coders 失效
标题翻译：从基于celp的语音编码器去除漩涡文物
公开(公告)号：US5633982A
公开(公告)日：1997-05-27
申请号：US734210
申请日：1996-10-21
申请人： Kalyan Ganesan , Ho Lee , Prabhat Gupta
发明人： Kalyan Ganesan , Ho Lee , Prabhat Gupta
IPC分类号： G10L19/00 , G10L19/12 , G10L21/02 , G10L9/00 , G10L5/06
CPC分类号： G10L19/012 , G10L19/12 , G10L19/135 , G10L2021/02168
摘要： The perception of speech processed by a CELP based coder, such as a VSELP coder, when operating in noisy background conditions is improved by removing swirl artifacts during silence periods. This is done by removing the low frequency components of the input signal when no speech is detected. A speech activity detector distinguishes between a periodic signal, like speech, and a non-periodic signal, like noise by using most of the VSELP coder internal parameters to determine the speech or non-speech conditions. To prevent the VSELP coder from determining pitches for non-periodic signals, a high pass filter is applied to the input signal to remove the pitch information for which the VSELP coder searches.
摘要翻译：当在噪声背景条件下操作时，由基于CELP的编码器（例如VSELP编码器）处理的语音的感知通过在静默期期间去除漩涡伪影来改善。这是通过在没有检测到语音时去除输入信号的低频分量来完成的。语音活动检测器通过使用大多数VSELP编码器内部参数来区分诸如语音的周期性信号和非周期性信号，如噪声，以确定语音或非语音条件。为了防止VSELP编码器确定非周期信号的间距，将高通滤波器应用于输入信号，以去除VSELP编码器搜索的音调信息。

123. 发明申请

US20140166703A1 LIQUID SPICE SUPPLY APPARATUS OF A COOKING GUIDE SYSTEM LINKED WITH THE INTERNET 审中-公开
标题翻译：与互联网连接的烹饪指南系统的液体食品供应设备
公开(公告)号：US20140166703A1
公开(公告)日：2014-06-19
申请号：US13823528
申请日：2011-09-14
申请人： Ho Lee
发明人： Ho Lee
IPC分类号： B05B7/00
CPC分类号： A47J43/04 , A47J36/321
摘要： The present invention relates to a liquid spice supply apparatus of a cooking guide system linked with the internet. The cooking guide system, including a digital chef provided by updating recipe information and an automatic spice supply part for storing spices and automatically supplying the spices to the outside, comprises: an air pump installed on the digital chef; a solenoid valve connected to the air pump to change a direction of supplied air; a plurality of spice containers connected to the solenoid valve to receive air and storing liquid spice; and a discharge hose pass through the liquid spice containers to discharge the liquid spice by means of the air supplied into the spice containers, wherein the liquid spice is supplied to the outside. Thus, the liquid spice stored in the liquid spice container may be supplied at more exact and precise amounts. Therefore, since an accurate amount of spice is supplied according to the provide recipe information and the number of portions, taste may always be uniformly maintained.
摘要翻译：本发明涉及一种与互联网连接的烹饪指南系统的液体香料供给装置。烹饪指南系统包括：通过更新配方信息提供的数字厨师和用于存储香料并自动将香料自动提供给外部的自动香料供应部件，包括：安装在数字厨师上的空气泵; 连接到空气泵以改变供给空气的方向的电磁阀; 连接到电磁阀的多个香料容器以接收空气并储存液体香料; 并且排出软管通过液体香料容器，通过供应到香料容器中的空气排出液体香料，其中将液体香料供应到外部。因此，储存在液体香料容器中的液体香料可以以更精确和精确的量供应。因此，由于根据提供配方信息和数量来提供精确量的香料，所以味道可以总是保持均匀。

124. 发明申请

US20140018943A1 SEASONING DISPENSING DEVICE FOR AN INTERNET-LINKED COOKING ASSISTANT SYSTEM 审中-公开
标题翻译：用于互联网烹饪辅助系统的调味分配装置
公开(公告)号：US20140018943A1
公开(公告)日：2014-01-16
申请号：US13823523
申请日：2011-09-14
申请人： Ho Lee
发明人： Ho Lee
IPC分类号： G06F17/00
CPC分类号： B65D83/0011 , A47J47/01
摘要： The present invention relates to an Internet-linked cooking assistant system that includes a digital chef providing continuously updated recipe information, and an automatic seasoning dispensing unit for storing and automatically dispensing seasonings to the outside, wherein the Internet-linked cooking assistant system comprises: seasoning containers respectively installed on the digital chef and defining a dispensing hole through which seasoning is dispensed; a screw shaft movably and rotatably installed on a dispensing hole of a seasoning container to open and close the dispensing hole; dispensing means coupled to the screw shaft and moving the screw shaft, so as to rotate the screw shaft and dispense seasoning; and rotating means for rotating the digital chef and selecting a seasoning container. By being able to supply a more accurate amount of seasoning stored in a seasoning container, a precise amount of seasoning can be dispensed according to provided cooking information and the number of servings, so that the same taste can always be replicated for a certain dish.
摘要翻译：本发明涉及一种互联网烹饪助理系统，其包括提供不断更新的配方信息的数字厨师，以及用于将调味料存储并自动分配到外部的自动调味分配单元，其中所述互联网烹饪辅助系统包括：调味料容器分别安装在数字厨师上，并且定义了分配孔，分配孔通过其分配; 丝杠轴可移动地并且可旋转地安装在调味容器的分配孔上以打开和关闭分配孔; 分配装置，联接到螺杆轴并移动螺杆轴，以便旋转螺杆轴并分配调味料; 以及用于旋转数字厨师并选择调味容器的旋转装置。通过能够提供储存在调味容器中的更精确量的调味料，可以根据提供的烹饪信息和份数分配精确量的调味料，使得对于某种菜肴总是可以复制相同的味道。

125. 发明授权

US08338261B2 Semiconductor device including field effect transistor and method of forming the same 有权
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US08338261B2
公开(公告)日：2012-12-25
申请号：US12851965
申请日：2010-08-06
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

126. 发明申请

US20120029490A1 DOSE DETERMINATION FOR INDUCING MICROCAVITATION IN RETINAL PIGMENT EPITHELIUM (RPE) 有权
标题翻译：诱导上皮细胞（RPE）中微量滴定的剂量测定
公开(公告)号：US20120029490A1
公开(公告)日：2012-02-02
申请号：US13145605
申请日：2010-01-22
申请人： Charles P. Lin , Clemens Alt , Ho Lee
发明人： Charles P. Lin , Clemens Alt , Ho Lee
IPC分类号： A61F9/008
CPC分类号： A61F9/008 , A61F9/00821 , A61F2009/00863
摘要： Methods and systems for controlling selective targeting of retinal pigment epithelium (RPE) cells within a treatment region of the RPE. The methods include (a) depositing a selected amount of energy on a test region of the RPE; (b) determining an extent to which microcavitation has occurred in the test region; and (c) on the basis of the determination, either depositing the selected amount of energy on the treatment region, or depositing an increased amount of energy on the test region, and repeating steps (b) and (c).
摘要翻译：用于控制RPE治疗区域内视网膜色素上皮细胞（RPE）细胞选择性靶向的方法和系统。这些方法包括（a）在RPE的测试区域上沉积选定量的能量; （b）确定在测试区域发生微气蚀的程度; 和（c）基于该确定，将所选择的能量沉积在处理区域上，或者在测试区域上沉积增加的能量，并重复步骤（b）和（c）。

127. 发明授权

US07879668B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07879668B2
公开(公告)日：2011-02-01
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

128. 发明申请

US20100233864A1 Methods of fabricating a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100233864A1
公开(公告)日：2010-09-16
申请号：US12656842
申请日：2010-02-17
申请人： Ho Lee , Moon-han Park , Hwa-sung Rhee , Myung-sun Kim , Hoi-sung Chung
发明人： Ho Lee , Moon-han Park , Hwa-sung Rhee , Myung-sun Kim , Hoi-sung Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/2236 , H01L21/265 , H01L21/76825 , H01L21/76829 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在衬底上形成栅极堆叠，在衬底上形成绝缘层以覆盖栅极堆叠，通过蚀刻绝缘层在栅极堆叠的两个侧壁处形成间隔物，以及在间隔物或绝缘层中离子注入杂质。

129. 发明授权

US07619285B2 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 失效
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US07619285B2
公开(公告)日：2009-11-17
申请号：US12029884
申请日：2008-02-12
申请人： Dong-suk Shin , Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Seung-hwan Lee
IPC分类号： H01L29/772 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a semiconductor substrate and which are formed by elevated epitaxial layers, each including a first epitaxial layer formed in a first recessed of the semiconductor substrate and a second epitaxial layer formed on the first epitaxial layer and extending to a level that is above an upper surface of the semiconductor substrate. The second conductivity type MOS transistor includes recessed source and drain regions which abut a channel region of the semiconductor substrate and which are formed by recessed epitaxial layers, each including a first epitaxial layer formed in a second recess of the semiconductor substrate and a second epitaxial layer formed in the second recess on the first epitaxial layer.
摘要翻译： CMOS晶体管包括第一和第二导电类型的MOS晶体管。第一导电型MOS晶体管包括升高的源极和漏极区域，其邻接半导体衬底中的沟道区域并且由升高的外延层形成，每个包括形成在半导体衬底的第一凹部中的第一外延层和第二外延层形成在所述第一外延层上并延伸到所述半导体衬底的上表面之上的水平。第二导电型MOS晶体管包括凹陷的源极和漏极区域，其邻接半导体衬底的沟道区域并且由凹陷的外延层形成，每个包括形成在半导体衬底的第二凹槽中的第一外延层和第二外延层形成在第一外延层上的第二凹槽中。

130. 发明授权

US07582535B2 Method of forming MOS transistor having fully silicided metal gate electrode 有权
标题翻译：形成具有完全硅化金属栅电极的MOS晶体管的方法
公开(公告)号：US07582535B2
公开(公告)日：2009-09-01
申请号：US11158978
申请日：2005-06-22
申请人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
发明人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.
摘要翻译：提供制造具有完全硅化金属栅电极的MOS晶体管的方法。该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。形成了跨越有源区域的绝缘栅极图案。在栅极图案的侧壁上形成间隔物。施加选择性外延生长工艺以在栅极图案上形成半导体层，并且在栅极图案的两侧形成半导体层。在这种情况下，在栅极图案上形成多晶半导体层，同时在栅极图案的两侧的有源区同时形成单晶半导体层。选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。将硅化处理应用于形成栅极减少图案的半导体衬底，以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式