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121. 发明授权

US06410384B1 Method of making an electric conductive strip 有权
公开(公告)号：US06410384B1
公开(公告)日：2002-06-25
申请号：US09795022
申请日：2001-02-26
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L21/743 , H01L21/76895 , H01L27/10885
摘要： A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Then, a CMP process is used to remove the ion-implanted-sensitive resist and the doped dielectric layer. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface.

122. 发明授权

US06376342B1 Method of forming a metal silicide layer on a source/drain region of a MOSFET device 有权
标题翻译：在MOSFET器件的源极/漏极区域上形成金属硅化物层的方法
公开(公告)号：US06376342B1
公开(公告)日：2002-04-23
申请号：US09671511
申请日：2000-09-27
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21425
CPC分类号： H01L21/02052 , H01L21/02238 , H01L21/02255 , H01L21/26506 , H01L21/28518 , H01L21/31662 , H01L29/6659
摘要： A process of forming a metal silicide layer, on a source/drain region of a MOSFET device, featuring ion implanted metal ions providing the metal component of the metal silicide layer, has been developed. After formation of a heavily doped source/drain region, in an area of a semiconductor region not covered by a insulator capped, gate structure, or by insulator spacers on the sides of the insulator capped gate structure, metal ions are implanted into the top surface of the heavily doped source/drain region. The metal ions are chosen from a group that includes titanium, tantalum, platinum, palladium, nickel and cobalt ions. An anneal procedure is then employed resulting in the formation of the metal silicide layer on the heavily doped source/drain region. Selective removal of unreacted metal ions is then accomplished via use wet etchant solutions. The use of implanted metal ions, when compared to a deposited metal layer, reduces the risk of unremoved metal, or formation of metal silicide ribbons, located on the surface of insulator, at the conclusion of the selective removal procedure, resulting in gate to substrate leakage or shorts.
摘要翻译：已经开发了在MOSFET器件的源极/漏极区域上形成金属硅化物层的工艺，其具有提供金属硅化物层的金属成分的离子注入的金属离子。在形成重掺杂的源极/漏极区之后，在未被绝缘体盖住的半导体区域的栅极结构或绝缘体封闭栅极结构的侧面上的绝缘体间隔物的区域中，金属离子被注入到顶表面的重掺杂源极/漏极区域。金属离子选自包括钛，钽，铂，钯，镍和钴离子的基团。然后使用退火程序，导致在重掺杂的源极/漏极区上形成金属硅化物层。然后通过使用湿蚀刻剂溶液来选择性去除未反应的金属离子。当与沉积的金属层相比时，使用植入的金属离子在选择性去除程序结束时降低了未被去除的金属或位于绝缘体表面上的金属硅化物带的形成的风险，导致栅极到衬底泄漏或短裤。

123. 发明授权

US06368973B1 Method of manufacturing a shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06368973B1
公开(公告)日：2002-04-09
申请号：US09668933
申请日：2000-09-25
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of manufacturing a shallow trench isolation structure. A pad oxide layer is formed on a substrate, and a mask layer is formed on the pad oxide layer. Next, using a photoresist having opening patterns as a mask, the mask layer and the pad oxide layer are etched, and a trench is formed within the substrate. Thereafter, the photoresist is laterally etched, thereby causing the photoresist openings to enlarge. Next, the mask layer exposed by the openings is etched, thereby forming a wide opening in the mask layer. Subsequently, the photoresist layer is removed, and the insulation layer is formed on the upper portion of the mask, within the wide opening and inside trench. Next, using the mask layer as the polishing stop layer, a chemical mechanical polish procedure is performed, thereby removing a portion of the insulation layer, exposing the mask layer and an even surface is achieved. Thereafter, the mask layer and a portion of the pad oxide layer are removed, thereby forming a T-shaped shallow trench isolation structure.
摘要翻译：一种制造浅沟槽隔离结构的方法。在衬底上形成衬垫氧化物层，并且在衬垫氧化物层上形成掩模层。接下来，使用具有开口图案的光致抗蚀剂作为掩模，蚀刻掩模层和焊盘氧化物层，并在衬底内形成沟槽。此后，光致抗蚀剂被横向蚀刻，从而使光致抗蚀剂开口增大。接下来，蚀刻由开口露出的掩模层，从而在掩模层中形成宽的开口。随后，去除光致抗蚀剂层，并且在宽开口和内沟槽内在掩模的上部形成绝缘层。接下来，使用掩模层作为抛光停止层，进行化学机械抛光程序，从而去除绝缘层的一部分，露出掩模层并实现均匀的表面。此后，去除掩模层和焊盘氧化物层的一部分，从而形成T形浅沟槽隔离结构。

124. 发明授权

US06358795B1 Method of making stacked capacitor in memory device 有权
标题翻译：在存储器件中制作叠层电容器的方法
公开(公告)号：US06358795B1
公开(公告)日：2002-03-19
申请号：US09661099
申请日：2000-09-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21242
CPC分类号： H01L28/91 , H01L28/84
摘要： The method of the invention contains providing a substrate, which has several conductive structures formed thereon. The conductive structure has a cap layer on top. A dielectric layer is formed over the substrate and the conductive structures. The dielectric layer is patterned to form an opening between the conductive structures to expose the substrate, the sidewalls of the conductive structures, and a portion of top surface of the conductive structures. A conductive plug fills the opening. A dielectric block formed on the conductive plug. A conductive spacer is formed on the sidewalls of the dielectric block, having electrical contact to the conductive plug. The dielectric block is removed to expose the conductive plug. A hemi-spherical grain (HSG) layer is formed on the topographic surface of the substrate. A dielectric spacer is formed on sidewall of the conductive spacer to cover a portion of the HSG layer. The dielectric spacer includes a material different to the dielectric layer in different etching ratio. An etching back process is performed to remove the HSG layer without being covered by the dielectric spacer. The dielectric spacer is removed. A second dielectric layer and a capacitor electrode layer are formed over the substrate.
摘要翻译：本发明的方法包括提供一种其上形成有多个导电结构的基底。导电结构在顶部具有盖层。介电层形成在衬底和导电结构之上。图案化电介质层以在导电结构之间形成开口，以露出衬底，导电结构的侧壁和导电结构的顶表面的一部分。导电塞填满开口。形成在导电插头上的介质块。在介电块的侧壁上形成导电间隔物，其与导电插塞具有电接触。去除介质块以露出导电插头。在衬底的地形表面上形成半球形颗粒（HSG）层。介电间隔物形成在导电间隔物的侧壁上以覆盖HSG层的一部分。电介质间隔物包括不同于不同蚀刻比的电介质层的材料。执行回蚀刻工艺以除去HSG层，而不被电介质间隔物覆盖。去除介电垫片。在基板上形成第二介质层和电容器电极层。

125. 发明授权

US06355538B1 Method of forming isolation material with edge extension structure 有权
标题翻译：用边缘延伸结构形成隔离材料的方法
公开(公告)号：US06355538B1
公开(公告)日：2002-03-12
申请号：US09664416
申请日：2000-09-18
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming an isolation trench structure wherein the dielectric material filling the trench extends beyond the trench edges thereby preventing gaps at the trench edges. A layer of first dielectric is formed on a silicon substrate and a layer of silicon, either polysilicon or amorphous silicon, or silicon nitride is formed on the layer of first dielectric. A resist mask having a trench opening is then formed on the layer of silicon or silicon nitride. An isotropic lateral etch, either a plasma isotropic lateral etch or a chemical wet etch, is then used to etch that part of said silicon or silicon nitride directly under the trench opening in the resist mask and to undercut the silicon or silicon nitride a first distance beyond the edge of the trench opening in the resist mask, thereby forming an oversize trench opening in the layer of silicon or silicon nitride. The trench opening is then transferred to the layer of first dielectric and a trench is formed in the silicon substrate. The resist mask is then removed and a layer of second dielectric is deposited. That part of the layer of second dielectric above the top surface of the layer of silicon or silicon nitride, the layer of silicon or silicon nitride, and the layer of first dielectric are then removed to complete the structure.
摘要翻译：形成隔离沟槽结构的方法，其中填充沟槽的介电材料延伸超过沟槽边缘，从而防止沟槽边缘处的间隙。在硅衬底上形成第一电介质层，并在第一电介质层上形成多晶硅或非晶硅或硅氮化硅层。然后在硅或氮化硅层上形成具有沟槽开口的抗蚀剂掩模。然后使用各向同性侧向蚀刻，等离子体各向同性横向蚀刻或化学湿式蚀刻，以直接在抗蚀剂掩模中的沟槽开口下蚀刻所述硅或氮化硅的那部分，并将硅或氮化硅底切第一距离超过抗蚀剂掩模中的沟槽开口的边缘，从而在硅或氮化硅层中形成一个大尺寸的沟槽开口。然后将沟槽开口转移到第一电介质层，并在硅衬底中形成沟槽。然后去除抗蚀剂掩模并沉积第二电介质层。然后去除硅或氮化硅层顶层表面上的第二电介质层，第一电介质层和第一电介质层，以完成该结构。

126. 发明授权

US06340614B1 Method of forming a DRAM cell 有权
标题翻译：形成DRAM单元的方法
公开(公告)号：US06340614B1
公开(公告)日：2002-01-22
申请号：US09678639
申请日：2000-10-03
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10852
摘要： A method of forming a DRAM cell is disclosed. A heavily-doped region is formed in a semiconductor substrate. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate in sequence. A trench is next formed in the semiconductor substrate and also forming source/drain regions. First spacers with dopant source material are formed on sidewalls of the trench. After forming a gate dielectric layer within the trench, a first plug is formed on the gate dielectric layer. After forming an isolation film on the first plug and forming source/drain extensions, a second plug is formed on the isolation film. After removing the second dielectric layer, second spacers and third spacers are formed on sidewalls of the first spacers. After removing the second spacers and upper portions of the first spacers, a capacitor is formed on the transistor.
摘要翻译：公开了一种形成DRAM单元的方法。在半导体衬底中形成重掺杂区域。依次在半导体衬底上形成第一电介质层和第二电介质层。接下来，在半导体衬底中形成沟槽并且还形成源极/漏极区域。具有掺杂剂源材料的第一间隔物形成在沟槽的侧壁上。在沟槽内形成栅极电介质层之后，在栅极电介质层上形成第一插头。在第一插头上形成隔离膜并形成源极/漏极延伸部之后，在隔离膜上形成第二插头。在去除第二电介质层之后，在第一间隔物的侧壁上形成第二间隔物和第三间隔物。在去除第一间隔物的第二间隔物和上部之后，在晶体管上形成电容器。

127. 发明授权

US06316815B1 Structure for isolating integrated circuits in semiconductor substrate and method for making it 有权
标题翻译：用于隔离半导体衬底中的集成电路的结构及其制造方法
公开(公告)号：US06316815B1
公开(公告)日：2001-11-13
申请号：US09277202
申请日：1999-03-26
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the semiconductor substrate. The dielectric stud is formed by depositing isolating material in a space defined by the trench and a dielectric layer overlying the semiconductor substrate and being partially removed over an area which spans the trench and extends over the lengthwise edges of the trench.
摘要翻译：建议用于隔离在半导体衬底中制造的集成电路的沟槽隔离结构，其特征在于在半导体衬底中填充并横跨沟槽的介质柱。电介质柱通过在由沟槽限定的空间中沉积隔离材料并且覆盖在半导体衬底上的介电层并且在跨越沟槽并在沟槽的纵向边缘上延伸的区域上被部分去除而形成。

128. 发明授权

US06312966B1 Method of forming sharp tip for field emission display 失效
标题翻译：形成锋利尖端的场发射显示方法
公开(公告)号：US06312966B1
公开(公告)日：2001-11-06
申请号：US09690909
申请日：2000-10-17
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2100
CPC分类号： H01J9/025
摘要： The present invention comprises forming a first conductive layer over the substrate to have a gap. A dielectric layer is then formed on the first conductive layer. A portion of the dielectric layer is removed to leave a residual dielectric layer in the gap. Next, isotropical etching is performed to etch the first conductive layer using the residual dielectric as an etching mask, thereby forming a conductive tip. A polishing stopper composed of oxide is formed over the conductive tip. A nitride layer is formed over the conductive tip and on the polishing stopper. The nitride is polished to the surface of the polishing stopper. A portion of the nitride layer is etched to form a step over the conductive tip. A second conductive layer is formed over the etched nitride layer. A portion of the second conductive layer is removed to expose an upper surface of the step. The nitride layer and the polishing stopper are respectively removed to expose the conductive tip.
摘要翻译：本发明包括在衬底上形成具有间隙的第一导电层。然后在第一导电层上形成电介质层。去除介电层的一部分以在间隙中留下残留的介电层。接下来，使用残留电介质作为蚀刻掩模来进行等温蚀刻以蚀刻第一导电层，由此形成导电尖端。在导电末端上形成由氧化物构成的抛光停止体。在导电末端和抛光停止器上形成氮化物层。将氮化物抛光到抛光止动器的表面。蚀刻氮化物层的一部分以在导电尖端上形成台阶。在蚀刻的氮化物层上形成第二导电层。去除第二导电层的一部分以露出台阶的上表面。分别去除氮化物层和抛光止动件以露出导电尖端。

129. 发明授权

US06294434B1 Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device 有权
标题翻译：在MOSFET器件的多晶硅栅极结构和源极/漏极区域上形成金属硅化物层的方法
公开(公告)号：US06294434B1
公开(公告)日：2001-09-25
申请号：US09670379
申请日：2000-09-27
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28044 , H01L21/28518
摘要： A process of forming a metal silicide layer, for a salicide gate structure, and forming a metal silicide layer for a MOSFET source/drain region, featuring ion implanted metal ions providing the metal component of the metal silicide layers, has been developed. After formation of a polysilicon gate structure, and of a heavily doped source/drain region, metal ions are implanted into a top portion of both the heavily doped source/drain region, and polysilicon gate structure. The metal ions are chosen from a group that includes titanium, tantalum, platinum, palladium, nickel and cobalt ions. A first anneal procedure is then employed resulting in the formation of the metal silicide layer on the heavily doped source/drain region, and formation of a salicide gate structure, comprised of metal silicide on the polysilicon gate structure. Selective removal of unreacted metal ions is then accomplished using wet etchant solutions, followed by a second anneal procedure, used to reduce the resistance of the metal silicide layers. The use of implanted metal ions, when compared to a blanket deposited metal layer, reduces the risk of unremoved metal, or formation of metal silicide ribbons, located on the surface of insulator, at the conclusion of the selective removal procedure, resulting in gate to substrate leakage or shorts.
摘要翻译：已经开发了用于硅化物栅极结构形成金属硅化物层并形成用于MOSFET源极/漏极区域的金属硅化物层的工艺，其特征在于提供金属硅化物层的金属成分的离子注入金属离子。在形成多晶硅栅极结构和重掺杂源极/漏极区之后，将金属离子注入到重掺杂源极/漏极区域和多晶硅栅极结构的顶部。金属离子选自包括钛，钽，铂，钯，镍和钴离子的基团。然后使用第一退火程序，导致在重掺杂的源极/漏极区上形成金属硅化物层，以及在多晶硅栅极结构上形成由金属硅化物构成的硅化物栅极结构。然后使用湿蚀刻剂溶液进行选择性去除未反应的金属离子，随后用第二退火方法来降低金属硅化物层的电阻。当与覆盖金属层相比时，使用植入的金属离子在选择性去除程序结束时降低了未被去除的金属或位于绝缘体表面上的金属硅化物带的形成的风险基板泄漏或短路。

130. 发明授权

US06281087B1 Process for fabricating metal silicide layer by using ion metal plasma deposition 有权
标题翻译：使用离子金属等离子体沉积法制造金属硅化物层的工艺
公开(公告)号：US06281087B1
公开(公告)日：2001-08-28
申请号：US09689158
申请日：2000-10-12
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/2855
摘要： The present invention provides a process for fabricating a metal silicide layer. First, a silicon substrate having a polysilicon gate region and source/drain regions thereon is provided. Then, a spacer is formed on a sidewall of the gate region. Then, a metal layer is formed on the gate region and the source/drain regions by using ion metal plasma (IMP) deposition with substantially no metal layer formed on the spacer. Finally, the metal layer is transformed into a metal silicide layer. By means of the process of the present invention, since substantially on metal or only trace metal is formed on the spacer, the unwanted metal silicide formed on the spacer can be effectively prevented, and the undesirable bridging effect can be greatly alleviated.
摘要翻译：本发明提供一种制造金属硅化物层的方法。首先，提供其上具有多晶硅栅极区域和源极/漏极区域的硅衬底。然后，在栅极区域的侧壁上形成间隔物。然后，通过使用离子金属等离子体（IMP）沉积，在栅极区域和源极/漏极区域上形成金属层，基本上没有在间隔物上形成金属层。最后，将金属层转变成金属硅化物层。通过本发明的方法，由于在间隔物上基本上形成金属或只有痕量金属，所以可以有效地防止形成在间隔物上的不需要的金属硅化物，从而可以大大减轻不希望的桥接效应。

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