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121. 发明申请

US20070130493A1 Feedback and Frame Synchronization between Media Encoders and Decoders 有权
标题翻译：媒体编码器和解码器之间的反馈和帧同步
公开(公告)号：US20070130493A1
公开(公告)日：2007-06-07
申请号：US11275071
申请日：2005-12-07
申请人： Warren Barkley , Regis Crinon , Chih-Lung Lin , Tim Moore , Wei Zhong , Minghui Xia
发明人： Warren Barkley , Regis Crinon , Chih-Lung Lin , Tim Moore , Wei Zhong , Minghui Xia
IPC分类号： H04L1/18 , G08C25/02
CPC分类号： H04L1/0014 , H04L1/0026 , H04L1/1835 , H04L1/1887 , H04N19/105 , H04N19/107 , H04N19/164 , H04N19/172 , H04N19/573 , H04N19/61 , H04N19/89 , H04N21/23439 , H04N21/25825 , H04N21/4331 , H04N21/6332 , H04N21/6336 , H04N21/654 , H04N21/6582
摘要： Feedback and frame synchronization between media encoders and decoders is described. More particularly, the encoder can encode frames that are based on source content to be sent to the decoder. The encoder can determine whether the frame should be cached by the encoder and the decoder. If the frame is to be cached, the encoder can so indicate by encoding the frame with one or more cache control bits. The decoder can receive the frame from the decoder, and can examine the cache control bits to determine whether to cache the frame. The decoder can also decode the frame.
摘要翻译：描述介质编码器和解码器之间的反馈和帧同步。更具体地，编码器可以将基于要发送到解码器的源内容的帧编码。编码器可以确定该帧是否应由编码器和解码器缓存。如果帧被缓存，编码器可以通过用一个或多个高速缓存控制位对帧进行编码来指示。解码器可以从解码器接收帧，并且可以检查高速缓存控制位以确定是否缓存帧。解码器也可以对帧进行解码。

122. 发明申请

US20070020953A1 Method for forming a high density dielectric film by chemical vapor deposition 有权
标题翻译：通过化学气相沉积法形成高密度电介质膜的方法
公开(公告)号：US20070020953A1
公开(公告)日：2007-01-25
申请号：US11186353
申请日：2005-07-21
申请人： Cheng-Yuan Tsai , Chih-Lung Lin , You-Hua Chou
发明人： Cheng-Yuan Tsai , Chih-Lung Lin , You-Hua Chou
IPC分类号： H01L21/31 , C23C8/00 , H01L21/469
CPC分类号： H01L21/31612 , C23C16/45523 , C23C16/45557 , C23C16/50 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/76801
摘要： A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)˜(d) are repeated until a high density dielectric film is formed on the substrate.
摘要翻译：一种通过化学气相沉积法形成高密度电介质膜的方法。该方法包括：（a）在处理室中设置基板; （b）第一气体以第一压力被引入处理室并吸附在衬底上，其中第一气体包含含硅或含碳气体; （c）第一气体停止，第一压力降低到第二压力; （d）第二气体以第三压力被引入处理室，并被迫与吸收在基板上的第一气体反应并保留在处理室中，其中第二气体包括氧化剂或还原剂; （e）重复步骤（b）〜（d），直到在基板上形成高密度电介质膜。

123. 发明授权

US07145172B2 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US07145172B2
公开(公告)日：2006-12-05
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： H01L31/0376 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

124. 发明授权

US07127114B2 Coded block pattern encoding with spatial prediction 有权
标题翻译：具有空间预测的编码块模式编码
公开(公告)号：US07127114B2
公开(公告)日：2006-10-24
申请号：US11323034
申请日：2005-12-30
申请人： Chih-Lung Lin , Ming-Chieh Lee
发明人： Chih-Lung Lin , Ming-Chieh Lee
IPC分类号： G06K9/36
CPC分类号： H04N19/20 , H04N19/157 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/186 , H04N19/196 , H04N19/197 , H04N19/46 , H04N19/463 , H04N19/51 , H04N19/593 , H04N19/61 , H04N19/70
摘要： The coded block parameters used to code blocks of image samples into structures called macroblocks are compressed more efficiently by exploiting the correlation between chrominance and luminance blocks in each macroblock. In particular, the coded block pattern for chrominance and luminance are combined into a single parameter for the macroblock and jointly coded with a single variable length code. To further enhance coding efficiency, the spatial coherence of coded block patterns can be exploited by using spatial prediction to compute predicted values for coded block pattern parameters.
摘要翻译：通过利用每个宏块中的色度和亮度块之间的相关性，将用于将图像样本的块编码为被称为宏块的结构的编码块参数被更有效地压缩。特别地，用于色度和亮度的编码块图案被组合成用于宏块的单个参数，并且用单个可变长度码共同编码。为了进一步提高编码效率，可以通过使用空间预测来计算编码块模式参数的预测值来利用编码块模式的空间相干性。

125. 发明申请

US20050037533A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050037533A1
公开(公告)日：2005-02-17
申请号：US10934014
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在氮化硅层上形成未掺杂的非晶硅层，ii）在未掺杂的非晶硅层上形成蚀刻掩模，以及iii）在未掺杂的非晶硅的部分上形成两个掺杂非晶硅层层和蚀刻掩模，两个掺杂的非晶硅层间隔开并位于栅极的任一侧，其中在电介质层上的未掺杂和掺杂的非晶硅层的蚀刻选择率不小于约5.0。

126. 发明申请

US20050032263A1 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor 有权
标题翻译：控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法
公开(公告)号：US20050032263A1
公开(公告)日：2005-02-10
申请号：US10934242
申请日：2004-09-03
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L21/00
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
摘要翻译：公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

127. 发明申请

US20050023533A1 Thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板
公开(公告)号：US20050023533A1
公开(公告)日：2005-02-03
申请号：US10932828
申请日：2004-09-02
申请人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
发明人： Chih-Yu Peng , Wei-Chuan Lin , Chian-Chih Hsiao , Ta-Ko Chuang , Chun-Hung Chu , Chih-Lung Lin , Chin-Mao Lin
IPC分类号： G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L29/423 , H01L29/04
CPC分类号： H01L27/1248 , G02F1/136213 , H01L27/1255 , H01L29/42384
摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
摘要翻译：提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

128. 发明授权

US06338668B1 In-line chemical mechanical polish (CMP) planarizing method employing interpolation and extrapolation 有权
标题翻译：采用插值和外插法的在线化学机械抛光（CMP）平面化方法
公开(公告)号：US06338668B1
公开(公告)日：2002-01-15
申请号：US09639864
申请日：2000-08-16
申请人： Chih-Lung Lin , Wen-Cheng Chien
发明人： Chih-Lung Lin , Wen-Cheng Chien
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B37/042 , B24B49/03
摘要： Within a chemical mechanical polish (CMP) method there is first provided a first control substrate, a first series of product substrates and a second control substrate. There is then sequentially chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the first control substrate to provide a planarized first control substrate, the first series of product substrates to provide a planarized first series of product substrates and the second control substrate to provide a planarized second control substrate. There is then determined, for the planarized first control substrate and the planarized second control substrate, a corresponding first value of a parameter within the chemical mechanical polish (CMP) planarizing method and a corresponding second value of the parameter within the chemical mechanical polish (CMP) planarizing method. There may then be interpolated or extrapolated from the first value of the parameter and the second value of the parameter to provide an interpolated value of the parameter for a planarized first product substrate within the planarized first series of product substrates or an extrapolated value of the parameter which may be employed for planarizing with enhanced uniformity a second product substrate within a second series of product substrates.
摘要翻译：在化学机械抛光（CMP）方法中，首先提供第一控制基板，第一系列产品基板和第二控制基板。然后依次进行化学机械抛光（CMP）平面化，同时采用化学机械抛光（CMP）平面化方法，第一控制基板提供平面化的第一控制基板，第一系列产品基板提供平面化的第一系列产品基板和第二控制基板，以提供平坦化的第二控制基板。然后，对于平坦化的第一控制基板和平坦化的第二控制基板，确定在化学机械抛光（CMP）平面化方法内的参数的对应的第一值和化学机械抛光（CMP）内的参数的对应的第二值）平面化方法。然后可以从参数的第一值和参数的第二值进行内插或外插，以提供平面化的第一系列产品基板内的平面化第一产品基板的参数的内插值，或参数的外推值其可以用于在第二系列产品基底内以均匀化的平面化第二产品基底。

129. 发明授权

US06315635B1 Method and apparatus for slurry temperature control in a polishing process 有权
标题翻译：抛光过程中浆料温度控制的方法和装置
公开(公告)号：US06315635B1
公开(公告)日：2001-11-13
申请号：US09283382
申请日：1999-03-31
申请人： Chih-Lung Lin
发明人： Chih-Lung Lin
IPC分类号： B24B4902
CPC分类号： B24B37/015 , B24B57/02
摘要： A method and an apparatus for controlling slurry temperature in a polishing machine, such as in a chemical mechanical polishing machine, are disclosed. In the method, an ambient temperature slurry is first provided to the surface of a polishing pad, the polishing process is then started with the polishing pad being rotated and intimately engaging a substrate mounted in a polishing head. By using at least two temperature sensors, the temperature of the slurry dispensed and the temperature of the polishing head are determined and sent to a temperature controller which in turn sends a signal to a heater for heating a slurry supply such that the temperature of the slurry being fed is the same as the temperature of the polishing pad. A heated slurry solution at substantially the same temperature of the polishing pad is then fed to the polishing pad for continuing the polishing process. The present invention novel apparatus includes at least two temperature sensors, a temperature controller and a heater or heat exchanger means for increasing the temperature of a slurry solution before it is fed to a polishing process.
摘要翻译：公开了一种用于控制抛光机中的浆料温度的方法和装置，例如在化学机械抛光机中。在该方法中，首先将环境温度浆料提供到抛光垫的表面，然后在抛光垫旋转并与安装在抛光头中的基板紧密接合的情况下开始抛光过程。通过使用至少两个温度传感器，分配的浆料的温度和抛光头的温度被确定并发送到温度控制器，温度控制器又将信号发送到用于加热浆料供应的加热器，使得浆料的温度被馈送与抛光垫的温度相同。然后在抛光垫的基本相同的温度下将加热的浆料溶液供给到抛光垫中，以继续抛光过程。本发明的新型装置包括至少两个温度传感器，温度控制器和加热器或热交换器装置，用于在将浆液提供给抛光过程之前提高浆液的温度。

130. 发明授权

US09856416B2 Phosphor and light emitting device 有权
公开(公告)号：US09856416B2
公开(公告)日：2018-01-02
申请号：US13158931
申请日：2011-06-13
申请人： Yuan-Ren Juang , Jen-Shrong Uen , Chih-Lung Lin
发明人： Yuan-Ren Juang , Jen-Shrong Uen , Chih-Lung Lin
IPC分类号： C09K11/08 , C09K11/77 , H01L33/50
CPC分类号： C09K11/0883 , C09K11/7734 , H01L33/502 , H01L2224/48091 , H01L2224/48247 , H01L2224/8592 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： The present invention provides a phosphor, including a constituent having the formula CapSrqMmAaBbOtNn:Zr, in which M selected from the group consisting of magnesium, barium, beryllium and zinc; A selected from the group consisting of aluminum, gallium, indium, scandium, yttrium, lanthanum, gadolinium and lutetium; B selected from the group consisting of silicon, germanium, tin, titanium, zirconium and hafnium; Z selected from the group consisting of europium and cerium; 0

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