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121. 发明授权

US5448578A Electrically erasable and programmable read only memory with an error check and correction circuit 失效
标题翻译：电可擦除和可编程只读存储器，带有错误检查和校正电路
公开(公告)号：US5448578A
公开(公告)日：1995-09-05
申请号：US38095
申请日：1993-03-30
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C17/00 , G06F11/10 , G11C16/06 , G11C29/00 , G11C29/42 , H03M13/00
CPC分类号： G06F11/1008 , G06F11/1076
摘要： An electrically erasable programmable read only memory (EEPROM), having error checking and correction circuitry uses a separation circuit to electrically isolate a temporary page buffer memory from a memory array so that better reliability of parity generation and error correction is provided. The EEPROM memory array includes a plurality of bit lines, a plurality of memory cells respectively connected to the bit lines and parity cells. The error check and correction circuit includes a column gate logic, connected to the plurality of bit lines, for temporarily loading randomly input data onto a memory page buffer. The EEPROM processes the data in the page buffer to logically store it as multi-byte data, simultaneously together with appropriate parity bit data corresponding to each multi-byte data set, in the memory array. Because data randomly input to and from the page buffer is selectively, electrically isolated from the memory array, bit errors that would otherwise be caused by defective memory cells, or bit lines, within the memory array, are compensated for in advance.
摘要翻译：具有错误检查和校正电路的电可擦除可编程只读存储器（EEPROM）使用分离电路将临时页缓冲存储器与存储器阵列电隔离，从而提供更好的奇偶校验生成和纠错的可靠性。 EEPROM存储器阵列包括多个位线，分别连接到位线和奇偶校验单元的多个存储器单元。错误检查和校正电路包括连接到多个位线的列门逻辑，用于临时将随机输入的数据装载到存储器页面缓冲器上。 EEPROM处理页缓冲器中的数据，以逻辑方式将其作为多字节数据存储，同时与对应于每个多字节数据集的适当奇偶校验位数据同时存储在存储器阵列中。由于随机地输入到页缓冲器中的数据与存储器阵列电隔离有选择地存在，否则将由存储器阵列内的缺陷存储器单元或位线引起的位错误被预先补偿。

122. 发明授权

US09484097B2 Multipage program scheme for flash memory 有权
标题翻译： Flash存储器的多程序方案
公开(公告)号：US09484097B2
公开(公告)日：2016-11-01
申请号：US13186789
申请日：2011-07-20
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/10 , G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline.
摘要翻译：一种用于在单个程序操作周期中将多个数据位数据编程到闪存单元的电路和方法。要编程到闪存阵列的一个物理页面中的多页数据被存储在存储器设备上的页面缓冲器或其他存储装置中。连接到要编程的单元的所选择的字线以不同的时间间隔以预定的程序配置被驱动，其中每个预定的程序配置文件被配置为将擦除阈值电压移位到对应于特定逻辑状态的特定阈值电压。响应于属于与该相应位线相关联的每一页数据的比特的特定逻辑状态的组合，多页位线控制器偏置每个位线以启用或禁止每个时间间隔期间的编程。

123. 发明授权

US08626958B2 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 失效
标题翻译：用于生产混合型串联互连设备的设备标识符的设备和方法
公开(公告)号：US08626958B2
公开(公告)日：2014-01-07
申请号：US13077168
申请日：2011-03-31
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
CPC分类号： G11C16/20 , G11C8/12
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。每个设备都有其设备类型的设备类型信息。包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

124. 发明申请

US20130176788A1 DEVICE SELECTION SCHEMES IN MULTI CHIP PACKAGE NAND FLASH MEMORY SYSTEM 有权
标题翻译：多芯片封装NAND闪存存储器系统中的器件选择方案
公开(公告)号：US20130176788A1
公开(公告)日：2013-07-11
申请号：US13611580
申请日：2012-09-12
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/06
CPC分类号： G11C15/046 , G11C7/109 , G11C8/12 , G11C16/0483 , G11C16/06 , G11C16/08
摘要： Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.
摘要翻译：提供了用于在多芯片封装NAND闪存系统中执行设备选择的系统和方法。在一些实施例中，存储器控制器通过命令执行设备选择。在其他实施例中，存储器控制器通过输入地址执行设备选择。

125. 发明授权

US08462551B2 Flash multi-level threshold distribution scheme 有权
公开(公告)号：US08462551B2
公开(公告)日：2013-06-11
申请号：US13328762
申请日：2011-12-16
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/34 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/344 , G11C16/3454 , G11C2211/5621
摘要： A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

126. 发明申请

US20130128668A1 NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE 有权
公开(公告)号：US20130128668A1
公开(公告)日：2013-05-23
申请号：US13743899
申请日：2013-01-17
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

127. 发明授权

US08406070B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US08406070B2
公开(公告)日：2013-03-26
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

128. 发明授权

US08405281B2 Transducer for ultrasonic diagnosis device and method for manufacturing the same 有权
标题翻译：超声诊断装置用传感器及其制造方法
公开(公告)号：US08405281B2
公开(公告)日：2013-03-26
申请号：US12717737
申请日：2010-03-04
申请人： Jin-Ki Kim , Jeong-chol Seo
发明人： Jin-Ki Kim , Jeong-chol Seo
IPC分类号： H01L41/08
CPC分类号： G10K11/004 , B06B1/0622
摘要： Disclosed is a transducer of an ultrasonic diagnosis device. Electrode patterns are formed inside a backing block, as one body, and thus, a prior art FPCB may be omitted.
摘要翻译：公开了一种超声波诊断装置的换能器。电极图案形成在背衬块内作为一体，因此可以省略现有技术的FPCB。

129. 发明申请

US20130039125A1 FLASH MEMORY PROGRAM INHIBIT SCHEME 审中-公开
公开(公告)号：US20130039125A1
公开(公告)日：2013-02-14
申请号：US13652947
申请日：2012-10-16
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

130. 发明申请

US20130033929A1 WRITE SCHEME IN A PHASE CHANGE MEMORY 审中-公开
标题翻译：相变记忆中的写入方案
公开(公告)号：US20130033929A1
公开(公告)日：2013-02-07
申请号：US13636547
申请日：2011-04-26
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/0061 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2013/0088 , G11C2213/72
摘要： In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is failed.
摘要翻译：在相变存储器中，接收与多个存储单元相对应的输入数据，并从多个存储单元读取先前的数据。将输入数据与先前的数据进行比较。在输入数据与多个存储单元中的一个或多个的先前数据不同且写入数小于最大值的情况下，多个存储器单元中的一个或多个用输入数据编程，并且写入计数更新或增加。重复数据比较和更新写入次数的这种操作。如果写入计数达到最大值，则确定写入失败。

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