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    • 112. 发明授权
    • INTEGRATED CIRCUIT
    • 集成电路
    • EP1020031B1
    • 2003-10-01
    • EP98945427.7
    • 1998-10-02
    • Cambridge Silicon Radio Limited
    • COLLIER, James, Digby, YarletSABBERTON, Ian, Michael
    • H03K23/54
    • H03K23/542
    • A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an input signal to be frequency divided, for modulating the propagation delay through each of the amplifier stages about the period of the input signal to be divided, such that when propagation through the odd amplifier stages increases, the propagation through the even amplifier stages decreases. The frequency divider circuit can be used as a pre-scaler of a radio receiver circuit.
    • 提供分频器电路,其具有与连接到第一放大器级的输入的最后放大器级的输出串联连接的偶数个放大器级; 以及响应要被分频的输入信号的调制装置,用于调制通过每个放大器级的关于要被分频的输入信号周期的传播延迟,使得当通过奇数放大器级的传播增加时,通过 甚至放大器级也会减少 分频器电路可以用作无线电接收器电路的预定标器。
    • 119. 发明公开
    • Single poly non-volatile memory cells
    • Einzel-Poly-NichtflüchtigeSpeicherzellen
    • EP2546877A1
    • 2013-01-16
    • EP12164564.2
    • 2012-04-18
    • Cambridge Silicon Radio Limited
    • Herberholz, Rainer
    • H01L27/115
    • H01L27/11558
    • A non-volatile memory cell comprising: a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor; wherein the coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. The word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.
    • 一种非易失性存储单元,包括:半导体衬底; 位于半导体衬底的第一有源区中的耦合电容器; 并且在所述半导体衬底的共享的第二有源区中,与所述读出晶体管的栅极并联配置的检测晶体管和隧穿电容器; 其中所述耦合电容器,感测晶体管和隧道电容器共享公共浮置栅电极,并且所述感测晶体管包括被布置成使得所述隧穿电容器由所述感测晶体管的所述浮置栅电极和漏极区域之间的重叠限定的源极和漏极区域。 字线触点可以是与耦合电容器分离的有效区域。 这个和/或其他特征可以帮助减少Frenkel-Poole传导。