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111. 发明授权

US07727830B2 Fabrication of germanium nanowire transistors 有权
标题翻译：锗纳米线晶体管的制造
公开(公告)号：US07727830B2
公开(公告)日：2010-06-01
申请号：US12006273
申请日：2007-12-31
申请人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
发明人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
IPC分类号： H01L21/337
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译：通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

112. 发明授权

US07713803B2 Mechanism for forming a remote delta doping layer of a quantum well structure 有权
标题翻译：用于形成量子阱结构的远程δ掺杂层的机理
公开(公告)号：US07713803B2
公开(公告)日：2010-05-11
申请号：US11731266
申请日：2007-03-29
申请人： Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Amlan Majumdar , Robert S. Chau
发明人： Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译：制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。

113. 发明申请

US20080237735A1 Hetero-Bimos injection process for non-volatile flash memory 有权
标题翻译：异质闪存注入过程
公开(公告)号：US20080237735A1
公开(公告)日：2008-10-02
申请号：US11731162
申请日：2007-03-30
申请人： Jack T. Kavalieros , Suman Datta , Robert S. Chau , David L. Kencke
发明人： Jack T. Kavalieros , Suman Datta , Robert S. Chau , David L. Kencke
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/28273 , H01L27/0705 , H01L29/0821 , H01L29/66825 , H01L29/73 , H01L29/7606 , H01L29/7881
摘要： A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.
摘要翻译：异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。衬底为双极晶体管提供硅发射极和含硅锗基底。反型层为双极晶体管提供硅集电极。

114. 发明申请

US20080116485A1 SB-BASED CMOS DEVICES 有权
标题翻译：基于SB的CMOS器件
公开(公告)号：US20080116485A1
公开(公告)日：2008-05-22
申请号：US11560494
申请日：2006-11-16
申请人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Mark L. Doczy , Robert S. Chau
发明人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Mark L. Doczy , Robert S. Chau
IPC分类号： H01L27/092
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/092
摘要： A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.
摘要翻译： III-V族材料CMOS器件可以具有通过它们的几个层基本上相同的NMOS和PMOS部分。这可能使CMOS器件易于制造并且防止NMOS和PMOS部分之间的热膨胀失配系数。

115. 发明申请

US20080017891A1 PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS 有权
标题翻译：密封层用于低电阻N型源漏管OHMIC接触
公开(公告)号：US20080017891A1
公开(公告)日：2008-01-24
申请号：US11480667
申请日：2006-06-30
申请人： Suman Datta , Jack T. Kavalieros , Robert S. Chau , Mark L. Doczy
发明人： Suman Datta , Jack T. Kavalieros , Robert S. Chau , Mark L. Doczy
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/0847 , H01L21/28525 , H01L29/7833
摘要： A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.
摘要翻译：一种包括N型晶体管结构的系统或装置，包括形成在衬底上的栅电极和形成在衬底中的源区和漏区; 与源区的联系; 以及钉扎层，其设置在所述源区域和所述第一触点之间并且限定所述钉扎层和所述源区域之间的界面，其中所述钉扎层在导带中具有施主型表面状态。一种包括在衬底上形成包括栅电极的晶体管结构和形成在衬底中的源极和漏极区的方法; 在源极和漏极区域上沉积具有施主型表面状态的钉扎层，使得在钉扎层与源极和漏极区域中的相应一个之间界定界面; 以及向所述源极区域形成第一接触和向所述漏极区域形成第二接触。

116. 发明申请

US20070232078A1 In situ processing for ultra-thin gate oxide scaling 审中-公开
标题翻译：用于超薄栅氧化物缩放的原位处理
公开(公告)号：US20070232078A1
公开(公告)日：2007-10-04
申请号：US11395853
申请日：2006-03-31
申请人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Robert S. Chau , Gilbert Dewey
发明人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Robert S. Chau , Gilbert Dewey
IPC分类号： H01L21/31
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and patterning a gate electrode structure comprising the gate electrode material.
摘要翻译：一种方法，包括在电介质材料上的衬底上沉积用于栅电极的材料，所述栅电极材料包括金属; 在不会促使与栅电极材料相关联的任何氧物质通过栅极电极材料移动到衬底的加工条件下，在栅电极材料上沉积封盖材料; 以及图案化包括栅电极材料的栅电极结构。

117. 发明授权

US08878363B2 Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same 有权
标题翻译：用于半导体器件的费米级裸露结构，其形成方法以及含有它们的体系
公开(公告)号：US08878363B2
公开(公告)日：2014-11-04
申请号：US12459254
申请日：2009-06-26
申请人： Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
发明人： Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L29/47 , H01L23/485 , H01L29/78 , H01L21/285 , H01L23/532 , H01L29/49 , H01L21/768 , H01L29/66
CPC分类号： H01L29/517 , H01B1/122 , H01L21/048 , H01L21/28525 , H01L21/324 , H01L21/76831 , H01L21/76834 , H01L21/76841 , H01L23/485 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L29/45 , H01L29/4966 , H01L29/512 , H01L29/518 , H01L29/66643 , H01L29/7839 , H01L29/7853 , H01L31/022466 , H01L31/022475 , H01L33/0041 , H01L33/40 , H01L45/08 , H01L45/1206 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L51/102 , H01L51/105 , H01L51/441 , H01L51/442 , H01L51/5203 , H01L51/5234 , H01L2251/301 , H01L2251/303 , H01L2251/306 , H01L2251/308 , H01L2924/0002 , H01L2924/00
摘要： An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
摘要翻译：使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。中间层可以是稀土氧化物。中间层可以是离子半导体。金属阻挡膜可以设置在中间层和金属耦合器之间。中间层可以是金属阻挡膜和半导体基板的热处理组合。形成中间层的方法可以包括对中间层进行分级。计算系统包括中间层。

118. 发明授权

US08294180B2 CMOS devices with a single work function gate electrode and method of fabrication 有权
标题翻译： CMOS器件具有单功能功能的栅电极和制造方法
公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

119. 发明授权

US08183556B2 Extreme high mobility CMOS logic 有权
标题翻译：极高移动性CMOS逻辑
公开(公告)号：US08183556B2
公开(公告)日：2012-05-22
申请号：US11305452
申请日：2005-12-15
申请人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/84
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

120. 发明授权

US08110458B2 Fabrication of germanium nanowire transistors 有权
标题翻译：锗纳米线晶体管的制造
公开(公告)号：US08110458B2
公开(公告)日：2012-02-07
申请号：US12762585
申请日：2010-04-19
申请人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
发明人： Been-Yih Jin , Jack T. Kavalieros , Matthew V. Metz , Marko Radosavlievic , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译：通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

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