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111. 发明申请

US20090241008A1 Memory devices and encoding and/or decoding methods 有权
标题翻译：存储器件和编码和/或解码方法
公开(公告)号：US20090241008A1
公开(公告)日：2009-09-24
申请号：US12379746
申请日：2009-02-27
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2903 , G06F11/1072 , H03M13/29 , H03M13/353
摘要： Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.
摘要翻译：提供存储器件和/或编码/解码方法。存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

112. 发明授权

US09158500B2 Device and method for processing data including generating a pseudo random number sequence 有权
标题翻译：用于处理数据的装置和方法，包括产生伪随机数序列
公开(公告)号：US09158500B2
公开(公告)日：2015-10-13
申请号：US13537297
申请日：2012-06-29
申请人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
发明人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
摘要翻译：一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

113. 发明授权

US08713411B2 Encoding and/or decoding memory devices and methods thereof 有权
标题翻译：编码和/或解码存储器件及其方法
公开(公告)号：US08713411B2
公开(公告)日：2014-04-29
申请号：US12232258
申请日：2008-09-12
申请人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
发明人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/03 , G06F11/1072 , H03M13/05
摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.
摘要翻译：可以提供编码/解码存储器件及其方法。根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

114. 发明授权

US08284599B2 Nonvolatile memory device and related programming method 有权
标题翻译：非易失性存储器件及相关编程方法
公开(公告)号：US08284599B2
公开(公告)日：2012-10-09
申请号：US12786724
申请日：2010-05-25
申请人： Han Woong Yoo , Jae Hong Kim , Jun Jin Kong
发明人： Han Woong Yoo , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3427 , G11C2211/5648
摘要： A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.
摘要翻译：一种对非易失性存储器件进行编程的方法包括编程连接到第一字线的存储器单元，连接到第二字线的编程存储器单元，连接到第一字线和第二字线之间的第三线的编程存储器单元，以及调整阈值电压连接到第一字线的存储器单元以补偿由连接到第三字线的存储器单元的编程所产生的干扰。

115. 发明申请

US20100251077A1 STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME 审中-公开
标题翻译：存储设备和包括其的数据存储系统
公开(公告)号：US20100251077A1
公开(公告)日：2010-09-30
申请号：US12729285
申请日：2010-03-23
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.
摘要翻译：存储装置包括控制器单元和存储单元阵列。控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。第一存储器具有与第二存储器不同的存储单元结构。

116. 发明授权

US08413011B2 Device and method providing 1-bit error correction 有权
标题翻译：提供1位纠错的装置和方法
公开(公告)号：US08413011B2
公开(公告)日：2013-04-02
申请号：US12651586
申请日：2010-01-04
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , H03M13/1105 , H03M13/1108
摘要： A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.
摘要翻译：提供1位纠错方法。在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点节点被更正。

117. 发明申请

US20100008146A1 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US20100008146A1
公开(公告)日：2010-01-14
申请号：US12453594
申请日：2009-05-15
申请人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
发明人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/24 , G11C2013/0073 , G11C2013/009 , G11C2013/0092
摘要： The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses.
摘要翻译：在存储器件中编程数据的方法包括将多个脉冲施加到多个存储器单元，所述多个脉冲中的至少一个是具有正电压的正脉冲，并且所述多个脉冲中的至少一个是负的具有负电压的脉冲和存在于所述多个脉冲的后续脉冲之间的时间间隔，并且控制所述多个脉冲中的至少一个时间间隔中的至少一个的幅度和至少一个的幅度中的至少一个。

118. 发明申请

US20090235128A1 Data detecting apparatus based on channel information and method thereof 审中-公开
标题翻译：基于信道信息的数据检测装置及其方法
公开(公告)号：US20090235128A1
公开(公告)日：2009-09-17
申请号：US12230502
申请日：2008-08-29
申请人： Heeseok Eun , Jun Jin Kong , Jae Hong Kim
发明人： Heeseok Eun , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/10 , G06F12/02 , G06F11/34
CPC分类号： G06F11/1008 , G11C16/26
摘要： An apparatus and a method for detecting data stored in a memory cell based on channel information of the memory cell are provided. The data detecting apparatus may include a voltage comparison unit that compares a plurality of soft decision reference voltages between neighboring hard decision reference voltages with a threshold voltage of a memory cell to determine a region including the threshold voltage, and a data detection unit that detects data stored in the memory cell based on channel information of the memory cell according to the region. The data detecting apparatus may further include a reference voltage determination unit that determines the plurality of soft decision reference voltages based on the channel information of the memory cell.
摘要翻译：提供了一种用于基于存储器单元的信道信息来检测存储在存储单元中的数据的装置和方法。数据检测装置可以包括电压比较单元，其将相邻硬判决参考电压之间的多个软判决参考电压与存储器单元的阈值电压进行比较，以确定包括阈值电压的区域;以及数据检测单元，其检测数据根据该区域，根据存储单元的信道信息存储在存储单元中。数据检测装置还可以包括参考电压确定单元，其基于存储器单元的信道信息来确定多个软判决参考电压。

119. 发明授权

US08984036B2 Methods for operating controllers using seed tables 有权
标题翻译：使用种子表操作控制器的方法
公开(公告)号：US08984036B2
公开(公告)日：2015-03-17
申请号：US13547212
申请日：2012-07-12
申请人： Yong June Kim , Jung Soo Chung , Jun Jin Kong , Hongrak Son
发明人： Yong June Kim , Jung Soo Chung , Jun Jin Kong , Hongrak Son
IPC分类号： G06F7/58
CPC分类号： G06F7/582
摘要： A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.
摘要翻译：用于操作控制器的方法可以包括将从PN序列发生器提供的伪噪声（PN）序列存储在种子表的第i个区域中，并将PN序列从第i个区域循环移位到第（i + 1个））表中的区域形成表。该表可能包括行和列区域。用于操作控制器的方法可以包括从序列发生器接收序列，将序列分解成种子单元，将分离序列存储在种子表的第j个区域中，以及形成包括与分离序列相对应的种子单元的表存储在第j个区域。用于操作控制器的方法可以包括将从序列生成器提供的序列存储在包括多个区域的种子表中，并且将表中的序列循环移位，直到在每个区域中形成种子。

120. 发明授权

US09875044B2 Data storage device compensating for initial threshold voltage distribution shift, method of operating the same, and data processing system including the same 有权
公开(公告)号：US09875044B2
公开(公告)日：2018-01-23
申请号：US14800783
申请日：2015-07-16
申请人： Dong Hwan Lee , Jun Jin Kong , Chang Kyu Seol , Hong Rak Son
发明人： Dong Hwan Lee , Jun Jin Kong , Chang Kyu Seol , Hong Rak Son
IPC分类号： G06F3/00 , G06F3/06 , G06F17/30 , G06F12/02 , G06F21/79 , G11C16/04
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0653 , G06F3/068 , G06F12/0246 , G06F17/3033 , G06F17/30867 , G06F21/79 , G11C16/0466
摘要： A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.

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