专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US08097910B2 Vertical transistors 有权
标题翻译：垂直晶体管
公开(公告)号：US08097910B2
公开(公告)日：2012-01-17
申请号：US12836459
申请日：2010-07-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
摘要翻译：本发明包括具有通过蚀刻半导体衬底形成的U形晶体管的半导体结构。在一个实施例中，晶体管的源极/漏极区域设置在由衬底中的交叉沟槽限定的柱对对的顶部。一个支柱通过在周围的沟槽上方延伸的脊连接到一对中的另一个柱。柱的脊和下部在U形结构的相对侧限定U形通道，面对在那些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。本发明还包括形成半导体结构的方法。

112. 发明申请

US20110303957A1 Concentric or Nested Container Capacitor Structure for Integrated Circuits 有权
标题翻译：集成电路的同心或嵌套集成电容器结构
公开(公告)号：US20110303957A1
公开(公告)日：2011-12-15
申请号：US13215529
申请日：2011-08-23
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/06
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L27/10855
摘要： Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.
摘要翻译：公开了容器电容器结构的实施例，其中至少两个容器电容器，例如内部和外部容器电容器被制成彼此相同并嵌套。嵌套电容器在一个实施例中通过在两个电容器接触插塞附近的嵌套容器电容器的介电层中限定一个孔而形成。通过对poly 1进行回蚀而形成外部电容器板，使其基本上留在孔的垂直边缘上并且与其中一个插塞接触。在聚合物1上形成至少一个牺牲侧壁，并且聚合物2沉积在侧壁上以形成与另一个插塞接触的内部电容器板。该结构被平坦化，牺牲侧壁被去除，形成电容器电介质并且被顶部覆盖3.另外的结构例如保护层（以防止聚1对聚2短路）和导电层插塞到它们各自的多层）也可以使用。

113. 发明授权

US08039348B2 Vertical gated access transistor 有权
标题翻译：垂直门控存取晶体管
公开(公告)号：US08039348B2
公开(公告)日：2011-10-18
申请号：US12785712
申请日：2010-05-24
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L27/088 , H01L21/76229 , H01L21/76232 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L29/66545 , H01L29/66795 , H01L29/7827 , H01L29/7851 , H01L29/7853
摘要： According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.
摘要翻译：根据本发明的一个实施例，一种形成装置的方法包括在衬底的第一区域中形成多个深沟槽和多个浅沟槽。至少一个浅沟槽位于两个深沟槽之间。多个浅沟槽和多个深沟槽彼此平行。该方法还包括在衬底的第一区域和第二区域上沉积导电材料层。该方法还包括蚀刻导电材料层以限定在衬底的第一区域上的多个间隙分开的多条线，以及在衬底的第二区域上方的多个有源器件元件。该方法还包括掩蔽衬底的第二区域。该方法还包括从衬底的第一区域去除多条线，从而形成多条暴露区域，多条线从该区域被去除。该方法还包括在衬底的第二区域被掩蔽的同时蚀刻多个暴露区域中的多个细长沟槽。

114. 发明申请

US20110143528A1 Devices with Cavity-Defined Gates and Methods of Making the Same 有权
标题翻译：具有腔定义门的设备及其制作方法
公开(公告)号：US20110143528A1
公开(公告)日：2011-06-16
申请号：US13028064
申请日：2011-02-15
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/28
CPC分类号： H01L29/7856 , H01L29/66545 , H01L29/66795 , H01L29/7827 , H01L29/7851
摘要： Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity.
摘要翻译：公开了方法，系统和装置，包括一种方法，其包括形成半导体鳍片的动作，在半导体鳍片附近形成牺牲材料，用电介质材料覆盖牺牲材料，通过从下面除去牺牲材料形成空腔电介质材料，并在腔中形成栅极。

115. 发明申请

US20110081757A1 MEMORY HAVING A VERTICAL ACCESS DEVICE 有权
标题翻译：具有垂直存取设备的存储器
公开(公告)号：US20110081757A1
公开(公告)日：2011-04-07
申请号：US12966582
申请日：2010-12-13
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L27/10823 , H01L21/84 , H01L21/86 , H01L27/10876
摘要： Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
摘要翻译：公开了具有垂直存取装置的半导体存储器件。在一些实施例中，一种形成该装置的方法包括在半导体衬底中设置一凹槽，其包括一对相对的侧壁和在相对的侧壁之间延伸的底板。电介质层可以沉积在凹槽的侧壁和底板上。可以在电介质层上形成导电膜并加工成从凹槽的地板选择性地去除膜并从对置的侧壁去除至少一部分导电膜。

116. 发明授权

US07807541B2 Concentric or nested container capacitor structure for integrated circuits 有权
标题翻译：用于集成电路的同心或嵌套容器电容器结构
公开(公告)号：US07807541B2
公开(公告)日：2010-10-05
申请号：US11449539
申请日：2006-06-07
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L27/10855
摘要： Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.
摘要翻译：公开了容器电容器结构的实施例，其中至少两个容器电容器，例如内部和外部容器电容器被制成彼此相同并嵌套。嵌套电容器在一个实施例中通过在两个电容器接触插塞附近的嵌套容器电容器的介电层中限定一个孔而形成。通过对poly 1进行回蚀而形成外部电容器板，使其基本上留在孔的垂直边缘上并且与其中一个插塞接触。在聚合物1上形成至少一个牺牲侧壁，并且聚合物2沉积在侧壁上以形成与另一个插塞接触的内部电容器板。该结构被平坦化，牺牲侧壁被去除，形成电容器电介质并且被顶部覆盖3.另外的结构例如保护层（以防止聚1对聚2短路）和导电层插塞到它们各自的多层）也可以使用。

117. 发明申请

US20090237996A1 MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS 有权
标题翻译：具有挥发性和非易失性记忆体的记忆结构
公开(公告)号：US20090237996A1
公开(公告)日：2009-09-24
申请号：US12052300
申请日：2008-03-20
申请人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
发明人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
IPC分类号： G11C11/34 , H01L29/78
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译：提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分行的存储单元。

118. 发明申请

US20090206443A1 DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME 有权
标题翻译：包括FIN晶体管的器件稳定地选择短路及其制造方法
公开(公告)号：US20090206443A1
公开(公告)日：2009-08-20
申请号：US12033780
申请日：2008-02-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/28 , H01L29/40
CPC分类号： H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851
摘要： Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench.
摘要翻译：公开了方法，系统和装置，包括一种方法，其包括蚀刻衬底中的行间沟槽的动作，基本上或完全地用电介质材料填充行间沟槽，并且至少形成鳍和绝缘突起部分地通过蚀刻衬底中的栅极沟槽。在一些实施例中，绝缘突起包括行间沟槽中的至少一些电介质材料。

119. 发明授权

US07573108B2 Non-planar transistor and techniques for fabricating the same 有权
标题翻译：非平面晶体管及其制造技术
公开(公告)号：US07573108B2
公开(公告)日：2009-08-11
申请号：US11433533
申请日：2006-05-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to a second voltage different than the first voltage. In some embodiments, the difference in voltage between the first voltage and the second voltage is greater than or substantially equal to a difference in voltage between the first voltage and a substrate voltage.
摘要翻译：非平面晶体管及其制造方法。在某些实施例中，晶体管包括有源栅极和无源栅极。有源栅极可以可切换地耦合到被配置为导通晶体管的第一电压，并且无源栅极可以固定地耦合到不同于第一电压的第二电压。在一些实施例中，第一电压和第二电压之间的电压差大于或基本上等于第一电压和基板电压之间的电压差。

120. 发明申请

US20090096000A1 DRAM CELLS WITH VERTICAL TRANSISTORS 有权
标题翻译：具有垂直晶体管的DRAM电池
公开(公告)号：US20090096000A1
公开(公告)日：2009-04-16
申请号：US12339610
申请日：2008-12-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
摘要翻译：本发明包括具有通过蚀刻半导体衬底形成的U形晶体管的半导体结构。在一个实施例中，晶体管的源极/漏极区域设置在由衬底中的交叉沟槽限定的柱对对的顶部。一个支柱通过在周围的沟槽上方延伸的脊连接到一对中的另一个柱。柱的脊和下部在U形结构的相对侧限定U形通道，面对在那些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。本发明还包括形成半导体结构的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式