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    • 111. 发明授权
    • Encoder including an error decision circuit
    • 编码器包括错误判定电路
    • US5274466A
    • 1993-12-28
    • US816651
    • 1992-01-03
    • Takashi IdaKenshi Dachiku
    • Takashi IdaKenshi Dachiku
    • G09C1/00G06T1/00G06T9/00G09C5/00H03M7/30H04N1/41H04N19/00H04N19/423H04N19/50H04N19/80H04N19/90H04N7/12
    • H04N19/00H04N19/98H04N19/99
    • An encoder comprises a memory for storing a to-be-coded original image, outputting a to-be-coded image signal in response to a to-be-coded region designation signal for designating a to-be-coded region used as a to-be-coded block, and outputting a to-be-transformed image signal in response to a to-be-transformed region designation signal for designating a to-be-transformed region; a transforming circuit for subjecting the to-be-transformed image signal to a predetermined transformation in response to a transformation method designation signal, and outputting a transformed image signal; a deciding circuit for deciding an error of the transformed image signal with reference to the to-be-coded image signal, and a control circuit for outputting, as a code, information on at least the to-be-transformed region and the transformation method which reduce the error decided by the deciding circuit to a predetermined value or below.
    • 编码器包括:存储器,用于存储待编码的原始图像,响应于要被编码的区域指定信号输出待编码的图像信号,用于指定被编码的区域用作为 并且响应于用于指定待变换区域的待变换区域指定信号而输出待变换图像信号; 变换电路,用于响应于变换方法指定信号对待变换的图像信号进行预定变换,并输出变换后的图像信号; 用于根据待编码的图像信号确定变换图像信号的误差的判定电路,以及用于输出至少要被变换的区域和变换方法的信息作为代码的控制电路 这将由判定电路决定的误差降低到预定值以下。
    • 116. 发明授权
    • Data storage apparatus and data writing/reading method
    • 数据存储装置和数据写入/读取方法
    • US08495468B2
    • 2013-07-23
    • US13014938
    • 2011-01-27
    • Kenshi Dachiku
    • Kenshi Dachiku
    • G11C29/00
    • G06F11/1044G06F11/108G06F2211/1057
    • According to one embodiment, a data storage apparatus including memory chips includes an error correction encoder, a RAID controller, error detectors and memory units. Each of the memory chips includes a semiconductor memory. The error correction encoder adds an error correction code to an encoded data stream. The RAID controller divides the encoded data stream from the error correction encoder into data blocks. The RAID controller generates a parity data block based on the data blocks. The RAID controller outputs the data blocks and parity data block to the error detectors, respectively. The error detectors add an error detection code to the data blocks and parity data block output from the RAID controller. Each of the memory units includes the memory chips. The memory units write the data blocks and parity data block from the error detectors to the memory chips.
    • 根据一个实施例,包括存储器芯片的数据存储装置包括纠错编码器,RAID控制器,错误检测器和存储器单元。 每个存储器芯片包括半导体存储器。 纠错编码器将纠错码添加到编码数据流中。 RAID控制器将来自纠错编码器的编码数据流分成数据块。 RAID控制器基于数据块生成奇偶校验数据块。 RAID控制器将数据块和奇偶校验数据块分别输出到错误检测器。 错误检测器向RAID控制器输出的数据块和奇偶校验数据块添加错误检测码。 每个存储器单元包括存储器芯片。 存储单元将数据块和奇偶校验数据块从错误检测器写入存储器芯片。
    • 117. 发明授权
    • Video server and seamless playback method
    • 视频服务器和无缝播放方式
    • US08428444B2
    • 2013-04-23
    • US13210071
    • 2011-08-15
    • Kenshi DachikuKenichi Kiura
    • Kenshi DachikuKenichi Kiura
    • H04N5/783
    • H04N21/44016H04N21/2365H04N21/4383
    • According to one embodiment, a video server includes a storage unit, an output processing unit, and a decoding processing unit. The storage unit stores first video data items and second video data items. The output processing unit generates first and second data blocks based on the first video data items and the second video data item read from the storage unit, respectively. The output processing unit outputs the first data blocks in fewer frames than usual, and outputs the second data block in vacant frame. The decoding processing unit decodes the first data blocks to generate a first playback signals, and outputs the first playback signals. The decoding processing unit stores the second data blocks.
    • 根据一个实施例,视频服务器包括存储单元,输出处理单元和解码处理单元。 存储单元存储第一视频数据项和第二视频数据项。 输出处理单元基于分别从存储单元读取的第一视频数据项和第二视频数据项生成第一和第二数据块。 输出处理单元以比通常更少的帧输出第一数据块,并将空白帧中的第二数据块输出。 解码处理单元解码第一数据块以产生第一重放信号,并输出第一重放信号。 解码处理单元存储第二数据块。