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111. 发明授权

US08873307B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08873307B2
公开(公告)日：2014-10-28
申请号：US13617856
申请日：2012-09-14
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/10 , G11C11/4097 , G11C11/4091 , G11C11/4096
CPC分类号： G11C11/4097 , G11C11/4091 , G11C11/4096 , G11C2207/002
摘要： A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address.
摘要翻译：半导体器件包括读出放大器，取决于地址，选择性地建立读出放大器与数据总线之间的电连接的晶体管; 连接到数据总线的写放大器，经由读出放大器，晶体管和数据总线从第一操作模式将数据从存储器单元输出到外部的外部端子，并经由写入放大器从外部向读出放大器提供数据，数据总线和处于第二操作模式的晶体管，以及向第一晶体管的栅电极提供电势的控制电路，其根据地址建立电连接。

112. 发明授权

US08638630B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US08638630B2
公开(公告)日：2014-01-28
申请号：US13620840
申请日：2012-09-15
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.
摘要翻译：一种设备包括多个恢复电路，每个恢复电路被提供用于相关联的一个本地位线，剩余的一个或多个恢复电路除了为选定的一个本地位线提供的恢复电路之外，还有一个恢复电路被配置为通过剩余的一个或本地位线中的一个，从存储器单元读取的数据或连接到其余一个或一个本地位线的单元的数据，并且通过剩余的一个或多个本地位线恢复数据进入连接到本地位线中剩余的一个或多个的存储器单元或单元。

113. 发明授权

US08624313B2 Method of manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08624313B2
公开(公告)日：2014-01-07
申请号：US13137701
申请日：2011-09-06
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/101 , G11C11/005 , G11C13/00 , G11C13/0007 , G11C13/0033 , G11C2213/31 , G11C2213/32 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的非易失性半导体存储元件，包括包括第一电极，可变电阻层和第二电极的层压体的可变电阻元件和易失性半导体存储元件形成在所述半导体基板上，包括电容元件，所述电容元件包括包含第三电极的层叠体，包含与所述可变电阻层相同的材料的电介质层和第四电极。

114. 发明授权

US08588019B2 Semiconductor device having current change memory cell 有权
标题翻译：具有电流变化存储单元的半导体器件
公开(公告)号：US08588019B2
公开(公告)日：2013-11-19
申请号：US13373005
申请日：2011-11-02
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/067 , G11C7/18 , G11C27/028
摘要： A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.
摘要翻译：半导体器件包括连接在位线和感测节点之间的第一晶体管和放大感测节点的信号的第二晶体管。控制施加到第一晶体管的栅极的第一电位，提供给感测节点的第二电位和提供给位线的第三电位，使得施加到第一晶体管的栅极的第一电位在第二和第二晶体管的栅极之间第三电位，第二电位被设定为大于第三电位，并且通过从第一电位减去第一晶体管的阈值电压而获得的预定电位小于第三电位并且高于提供给第二晶体管的低电位。根据当前变化存储单元的数据，位线的电位从第三电位转向低电位。

115. 发明授权

US08509020B2 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US08509020B2
公开(公告)日：2013-08-13
申请号：US12929899
申请日：2011-02-23
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1045 , G11C11/4087 , G11C11/4096 , G11C2207/107
摘要： A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.
摘要翻译：数据处理系统包括具有多个块的第一半导体器件，每个块包括多个数据;以及第二半导体器件，其具有控制第一半导体器件的第一控制电路，并且第一控制电路发出多个命令以与所述第一半导体器件以接入单元为单位，包括分别定义指示不同数据的数目的多个突发长度的多个第一定义，以及多个第二定义，其定义包括在各个块和分别构成突发长度的不同数据的数量的排列顺序，并且根据第一和第二定义通过多个不同数据的数据与第一半导体器件通信。

116. 发明授权

US08441840B2 Semiconductor device and data processing system 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US08441840B2
公开(公告)日：2013-05-14
申请号：US13006109
申请日：2011-01-13
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C8/12 , G11C11/24 , G11C11/404 , G11C11/4091 , G11C2211/4016
摘要： A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.
摘要翻译：半导体器件包括具有电容器的存储单元和具有浮体结构的选择晶体管，连接到选择晶体管的位线，位线控制电路和放大从存储单元读出的信号的读出放大器。位线控制电路在存储单元的非访问周期期间将位线设置为第一电位，然后在存储单元的访问周期期间将位线设置为第二电位。从而，可以通过减少存储单元的数据存储节点处的泄漏电流来延长数据保持时间，从而可以减少用于数据保持的平均消耗电流。

117. 发明申请

US20130107650A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE 有权
标题翻译：具有分层线结构的半导体器件
公开(公告)号：US20130107650A1
公开(公告)日：2013-05-02
申请号：US13620840
申请日：2012-09-15
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.
摘要翻译：一种设备包括多个恢复电路，每个恢复电路被提供用于相关联的一个本地位线，剩余的一个或多个恢复电路除了为选定的一个本地位线提供的恢复电路之外，还有一个恢复电路被配置为通过剩余的一个或本地位线中的一个，从存储器单元读取的数据或连接到其余一个或一个本地位线的单元的数据，并且通过剩余的一个或多个本地位线恢复数据进入连接到本地位线中剩余的一个或多个的存储器单元或单元。

118. 发明授权

US08422316B2 Semiconductor device and data processing system 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US08422316B2
公开(公告)日：2013-04-16
申请号：US12929531
申请日：2011-01-31
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/00
摘要： A semiconductor device comprises a bit line transmitting a signal to be sensed, a single-ended sense amplifier sensing and amplifying the signal transmitted from the bit line to the input node, and a reference voltage supplying circuit outputting a reference voltage. The sense amplifier includes a first transistor for charge transfer between the bit line and an input node, and the voltage value of the reference voltage is controlled in association with a threshold voltage of the first transistor. The reference voltage is set to a first logical value of the transfer control signal which controlled to be first and second logical values.
摘要翻译：半导体器件包括发送要感测的信号的位线，感测并放大从位线发送到输入节点的信号的单端读出放大器，以及输出参考电压的参考电压供给电路。读出放大器包括用于位线和输入节点之间的电荷转移的第一晶体管，并且与第一晶体管的阈值电压相关联地控制参考电压的电压值。参考电压被设置为被控制为第一和第二逻辑值的传送控制信号的第一逻辑值。

119. 发明申请

US20120147686A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE AND CONTROL METHOD THEREOF 有权
标题翻译：具有分层线结构的半导体器件及其控制方法
公开(公告)号：US20120147686A1
公开(公告)日：2012-06-14
申请号：US13313731
申请日：2011-12-07
申请人： Shinichi TAKAYAMA , Kazuhiko Kajigaya
发明人： Shinichi TAKAYAMA , Kazuhiko Kajigaya
IPC分类号： G11C7/12
CPC分类号： G11C11/4097 , G11C7/12 , G11C11/4074 , G11C11/4094
摘要： Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.
摘要翻译：这里公开了包括全局位线和局部位线的半导体器件，以及耦合在其间的开关。在执行预充电操作时，通过使开关接通来向全局位线提供预充电电压，使得局部位线通过全局位线和开关接收预充电电压，并且在经过预定时间之后，在本地位线进一步提供预充电电压，而不需要全局位线和开关的干预。

120. 发明申请

US20120113735A1 Semiconductor device having current change memory cell 有权
标题翻译：具有电流变化存储单元的半导体器件
公开(公告)号：US20120113735A1
公开(公告)日：2012-05-10
申请号：US13373005
申请日：2011-11-02
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/067 , G11C7/18 , G11C27/028
摘要： A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.
摘要翻译：半导体器件包括连接在位线和感测节点之间的第一晶体管和放大感测节点的信号的第二晶体管。控制施加到第一晶体管的栅极的第一电位，提供给感测节点的第二电位和提供给位线的第三电位，使得施加到第一晶体管的栅极的第一电位在第二和第二晶体管的栅极之间第三电位，第二电位被设定为大于第三电位，并且通过从第一电位减去第一晶体管的阈值电压而获得的预定电位小于第三电位并且高于提供给第二晶体管的低电位。根据当前变化存储单元的数据，位线的电位从第三电位转向低电位。

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