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111. 发明申请

US20050029660A1 Adhesions of structures formed from materials of poor adhesion 审中-公开
标题翻译：由粘附性差的材料形成的结构的粘附
公开(公告)号：US20050029660A1
公开(公告)日：2005-02-10
申请号：US10899444
申请日：2004-07-26
申请人： Eike Ruttkowski , Franz Hofmann , Bjorn-Oliver Eversmann
发明人： Eike Ruttkowski , Franz Hofmann , Bjorn-Oliver Eversmann
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , B05D5/12 , H01L21/4763 , H01L23/52
CPC分类号： H01L21/7685 , H01L21/76841 , H01L21/76867 , H01L23/5283 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device having a substrate, at least one adhesion promoter core, which is deposited on a part of the substrate, and a deposit, which completely surrounds the adhesion promoter core, of a material of poor adhesion which is different than the adhesion promoter material and is in direct contact with the substrate, as well as methods-for the production thereof.
摘要翻译：具有衬底，沉积在基底的一部分上的至少一个粘合促进剂芯和完全包围粘合促进剂芯的沉积物，其粘附力不同于粘合促进剂材料和与基底直接接触，以及用于其生产的方法。

112. 发明授权

US06798014B2 Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore 失效
标题翻译：因此，半导体存储单元和半导体元件以及制造方法
公开(公告)号：US06798014B2
公开(公告)日：2004-09-28
申请号：US10140393
申请日：2002-05-07
申请人： Till Schloesser , Franz Hofmann
发明人： Till Schloesser , Franz Hofmann
IPC分类号： H01L29788
CPC分类号： H01L27/108 , G11C11/404 , G11C11/405 , H01L27/10823 , H01L27/10876
摘要： A semiconductor memory cell with a storage transistor, a selection transistor and a layer structure is provided. The layer structure is formed of at least two semiconductor layers separated from one another by a dielectric. A control electrode that controls a current flow through the layer structure is arranged at at least one end face of the layer structure. The layer structure forms what is referred to as a PLED device.
摘要翻译：提供具有存储晶体管，选择晶体管和层结构的半导体存储单元。层结构由通过电介质彼此分离的至少两个半导体层形成。控制电流通过层结构的控制电极设置在层结构的至少一个端面。层结构形成所谓的PLED设备。

113. 发明授权

US06362502B1 DRAM cell circuit 有权
标题翻译： DRAM单元电路
公开(公告)号：US06362502B1
公开(公告)日：2002-03-26
申请号：US09692118
申请日：2000-10-19
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876
摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.
摘要翻译：存储单元包含存储晶体管和转移晶体管。转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。控制栅电极通过第二电介质层与浮置栅电极隔离。存储晶体管的第一源/漏区连接到位线。存储器和转移晶体管优选地具有不同的导电类型。在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

114. 发明授权

US6111267A CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer 失效
标题翻译： CMOS集成电路包括形成掺杂阱，本征硅层，锗在25％至50％之间的应力硅锗层和另一本征硅层
公开(公告)号：US6111267A
公开(公告)日：2000-08-29
申请号：US71153
申请日：1998-05-04
申请人： Hermann Fischer , Franz Hofmann
发明人： Hermann Fischer , Franz Hofmann
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8256 , H01L27/06 , H01L27/092 , H01L29/06
CPC分类号： H01L21/8256 , H01L21/823807 , H01L27/0605 , H01L27/092
摘要： An integrated CMOS circuit, and method for producing same, including a semiconductor substrate having a p-channel MOS transistor and an n-channel MOS transistor formed therein and having a first silicon layer, a stressed Si.sub.1-x Ge.sub.x layer and a second silicon layer which are preferably grown by selective epitaxy. In an ON state, a buried channel is formed in the stressed Si.sub.1-x Ge.sub.x layer in the p-channel MOS transistor and a surface channel is formed in the second silicon layer in the n-channel MOS transistor.
摘要翻译：一种集成CMOS电路及其制造方法，包括：在其中形成有p沟道MOS晶体管和n沟道MOS晶体管的半导体衬底，其具有第一硅层，应力Si 1-x Ge x层和第二硅层，优选通过选择性外延生长。在导通状态下，在p沟道MOS晶体管的受应力的Si1-xGex层中形成掩埋沟道，在n沟道MOS晶体管的第二硅层中形成表面沟道。

115. 发明授权

US6049105A DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing same 失效
标题翻译：具有动态自放大存储单元的DRAM单元布置及其制造方法
公开(公告)号：US6049105A
公开(公告)日：2000-04-11
申请号：US89539
申请日：1998-06-03
申请人： Wolfgang Krautschneider , Franz Hofmann
发明人： Wolfgang Krautschneider , Franz Hofmann
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/108 , H01L27/10876
摘要： A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as vertical MOS transistors and are arranged one over the other such that they are connected to one another via a common source/drain region. A source/drain region of the memory transistor is connected to a supply voltage line, a source/drain region of the selection transistor is connected to a bitline, and the gate electrode of the selection transistor is connected to a wordline. A diode structure is connected between the common source/drain region and the gate electrode of the memory transistor.
摘要翻译：具有动态，自放大存储单元的DRAM单元布置及其制造方法，其中每个存储单元包括选择晶体管，存储晶体管和二极管结构。选择晶体管和存储晶体管各自被形成为垂直MOS晶体管，并且彼此重叠地布置成使得它们经由公共源极/漏极区彼此连接。存储晶体管的源极/漏极区域连接到电源电压线，选择晶体管的源极/漏极区域连接到位线，并且选择晶体管的栅极电极连接到字线。在公共源极/漏极区域和存储晶体管的栅电极之间连接二极管结构。

116. 发明授权

US6044009A DRAM cell arrangement and method for its production 有权
标题翻译： DRAM单元布置及其生产方法
公开(公告)号：US6044009A
公开(公告)日：2000-03-28
申请号：US274733
申请日：1999-03-23
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/04
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F.sup.2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

117. 发明授权

US5998261A Method of producing a read-only storage cell arrangement 失效
标题翻译：制造只读存储单元布置的方法
公开(公告)号：US5998261A
公开(公告)日：1999-12-07
申请号：US973701
申请日：1997-12-08
申请人： Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider , Lothar Risch
发明人： Franz Hofmann , Wolfgang Rosner , Wolfgang Krautschneider , Lothar Risch
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11517 , H01L27/115
摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.
摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。第WO97 / 02599号公报日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。具有存储单元的单元阵列设置在半导体基板的主表面上。每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。多个基本上平行的带状沟槽设置在单元阵列中。垂直MOS晶体管布置在沟槽的侧面。存储单元在每种情况下都布置在沟槽的相对侧面上。

118. 发明授权

US5920099A Read-only memory cell array and process for manufacturing it 失效
标题翻译：只读存储单元阵列及其制造过程
公开(公告)号：US5920099A
公开(公告)日：1999-07-06
申请号：US913332
申请日：1997-09-11
申请人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
发明人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.
摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。

119. 发明授权

US5710072A Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells 失效
标题翻译：包含自放大动态MOS晶体管存储单元的制造和布置方法
公开(公告)号：US5710072A
公开(公告)日：1998-01-20
申请号：US737236
申请日：1996-11-18
申请人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
发明人： Wolfgang Krautschneider , Lothar Risch , Franz Hofmann
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.
摘要翻译： PCT No.PCT / EP95 / 01656 Sec。 371日期：1996年11月18日 102（e）1996年11月18日PCT PCT 1995年5月2日PCT公布。公开号WO95 / 31828 日期：1995年11月23日为了制造包含自放大动态MOS晶体管存储单元的布置，每个包括选择晶体管，存储晶体管和二极管结构，选择晶体管和存储晶体管通过公共节点串联连接，二极管结构连接在存储晶体管的公共节点和栅电极（10）之间，选择晶体管和存储晶体管形成为垂直MOS晶体管。为此，产生其中产生沟槽（5,6）并且设置有栅极电介质（7,8）和栅电极（9,10））的适当掺杂区（2,3,4）的垂直序列，特别是通过LPCVD外延或通过分子束外延。

120. 发明授权

US4274360A Apparatus for regenerating used foundry sand 失效
标题翻译：用于再生铸造砂的设备
公开(公告)号：US4274360A
公开(公告)日：1981-06-23
申请号：US26891
申请日：1979-04-04
申请人： Franz Hofmann , Franz Satmer
发明人： Franz Hofmann , Franz Satmer
IPC分类号： B22C5/02 , B01F9/08 , B02C17/10 , B22C5/04 , B22C5/10 , B05C5/00
CPC分类号： B22C5/04 , B01F9/08 , B22C5/10 , Y10S241/10
摘要： Regeneration of clay-bonded used foundry sand for reuse instead of new sand. A dry mass of used sand is rubbed for such a length of time, is accelerated suddenly and delayed, and is freed continuously of fine components, until the fine matter, active bonding clay and oolitization degree fall below certain threshold values such that the regenerated product substantially gains the characteristics of new sand. An apparatus for regeneration treatment contains a horizontal revolving sand drum (10), an impact rotor (30) disposed inside said drum in the area of the fall stream (46) of the used sand and a pneumatic dust removal device (36) disposed in the inside of the drum. A chemical secondary treatment of the regenerated product can be carried out advantageously in the same installation in order to bind remaining fine matter to the surface of the grains of sand and simultaneously to seal the pores of the grains.
摘要翻译：使用粘土的旧铸造砂再生再利用而不是新砂。二手沙的干质量摩擦一段时间，加速突然延迟，并连续释放精细成分，直到细小，活性粘土和鲕粒度低于某一阈值，使再生产品大大增加了新沙的特点。一种用于再生处理的装置包括水平旋转砂轮（10），设置在所述滚筒内部的冲击转子（30），所述冲击转子（30）位于所述用过的砂的下落流（46）的区域中，以及气动除尘装置（36）鼓里面。再生产物的化学二次处理可以在相同的装置中有利地进行，以将剩余的细颗粒与砂粒的表面结合，同时密封颗粒的孔。

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