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111. 发明申请

US20060281236A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
标题翻译：提高6T CMOS SRAM单元的稳定性的方法和装置
公开(公告)号：US20060281236A1
公开(公告)日：2006-12-14
申请号：US11508009
申请日：2006-08-21
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： H01L21/84
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
摘要翻译：本发明是包括两个存取装置的CMOS SRAM单元，每个存取装置由具有单个鳍片的三栅晶体管组成; 两个上拉装置，每个上拉装置由具有单个鳍片的三栅极晶体管组成; 和两个下拉器件，每个下拉器件由具有多个鳍片的三栅晶体管组成。还提供了一种用于制造包括双鳍三栅极晶体管的CMOS SRAM单元的方法。

112. 发明申请

US20050237850A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
公开(公告)号：US20050237850A1
公开(公告)日：2005-10-27
申请号：US11165724
申请日：2005-06-24
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： G11C11/412 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/786 , G11C8/02
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

113. 发明申请

US20060228840A1 Tri-gate devices and methods of fabrication 有权
公开(公告)号：US20060228840A1
公开(公告)日：2006-10-12
申请号：US11297084
申请日：2005-12-07
申请人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott Hareland
发明人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott Hareland
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66795 , H01L29/772 , H01L29/7854 , H01L29/78645 , H01L29/78696 , H01L51/0048 , H01L51/0554 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

114. 发明申请

US20050199950A1 Tri-gate devices and methods of fabrication 有权
公开(公告)号：US20050199950A1
公开(公告)日：2005-09-15
申请号：US11123565
申请日：2005-05-06
申请人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott Hareland
发明人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott Hareland
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/76 , H01L29/94
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66795 , H01L29/772 , H01L29/7854 , H01L29/78645 , H01L29/78696 , H01L51/0048 , H01L51/0554 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

115. 发明申请

US20050073060A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
公开(公告)号：US20050073060A1
公开(公告)日：2005-04-07
申请号：US10679124
申请日：2003-10-02
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： G11C11/412 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/786
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

116. 发明授权

US07494862B2 Methods for uniform doping of non-planar transistor structures 有权
标题翻译：均匀掺杂非平面晶体管结构的方法
公开(公告)号：US07494862B2
公开(公告)日：2009-02-24
申请号：US11529963
申请日：2006-09-29
申请人： Brian Doyle , Robert Chau , Suman Datta , Jack Kavalieros
发明人： Brian Doyle , Robert Chau , Suman Datta , Jack Kavalieros
IPC分类号： H01L21/8238
CPC分类号： H01L21/823437 , H01L21/2236 , H01L21/26586 , H01L29/66803 , H01L29/7851
摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.
摘要翻译：用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。可以去除掩模，从而产生均匀掺杂的硅体。

117. 发明申请

US20070034972A1 Tri-gate devices and methods of fabrication 有权
标题翻译：三栅极器件和制造方法
公开(公告)号：US20070034972A1
公开(公告)日：2007-02-15
申请号：US11588066
申请日：2006-10-25
申请人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta
发明人： Robert Chau , Brian Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66795 , H01L29/772 , H01L29/7854 , H01L29/78645 , H01L29/78696 , H01L51/0048 , H01L51/0554 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.
摘要翻译：本发明是一种半导体器件，其包括碳纳米管体，其具有形成在基底上的顶表面和侧向相对的侧壁。栅极电介质层形成在碳纳米管体的上表面和碳纳米管体的横向相对侧壁上。栅极电极形成在碳纳米管主体的顶表面上的栅极电介质上并且与碳纳米管体的横向相对的侧壁上的栅电介质相邻。

118. 发明申请

US20070134878A1 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US20070134878A1
公开(公告)日：2007-06-14
申请号：US11299102
申请日：2005-12-09
申请人： Justin Brask , Jack Kavalieros , Brian Doyle , Robert Chau
发明人： Justin Brask , Jack Kavalieros , Brian Doyle , Robert Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

119. 发明授权

US06998686B2 Metal-gate electrode for CMOS transistor applications 失效
标题翻译：用于CMOS晶体管应用的金属栅电极
公开(公告)号：US06998686B2
公开(公告)日：2006-02-14
申请号：US10230944
申请日：2002-08-28
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.
摘要翻译：描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。栅电极结构具有三层金属栅电极和多晶硅层。第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。第二金属层用于设定栅电极结构的功函数。第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

120. 发明授权

US07936025B2 Metalgate electrode for PMOS transistor 有权
标题翻译：用于PMOS晶体管的金属栅电极
公开(公告)号：US07936025B2
公开(公告)日：2011-05-03
申请号：US11231437
申请日：2005-09-20
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.
摘要翻译：描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。栅电极结构具有三层金属栅电极和多晶硅层。第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。第二金属层用于设定栅电极结构的功函数。第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

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