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101. 发明公开

EP2884395A3 Storage system having data storage lines with different data storage line sizes 审中-公开
标题翻译： Speichersystem mit Datenspeicherleitungen mit unterschiedlichenDatenspeicherleitungsgrößen
公开(公告)号：EP2884395A3
公开(公告)日：2015-10-07
申请号：EP14151635.1
申请日：2014-01-17
申请人： MediaTek Singapore Pte Ltd.
发明人： Huang, Hsilin
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0886 , G06F2212/455 , G06F2212/601 , G06F2212/6032
摘要： A storage system (200) includes a data storage device (112) having a plurality of data storage lines (113), a tag storage device (114) having a plurality of address tags (115, 116) each associated with one data storage line (113) allocated in the data storage device (112), and a controller (117). The controller (117) sets a first number of address tags (115, 116) and configures a first number of data storage lines (113) to serve as a first data storage line with a first data storage line size, and sets a second number of address tags (115, 116) and configures a second number of data storage lines (113) to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.
摘要翻译：存储系统（200）包括具有多个数据存储线（113）的数据存储设备（112），具有多个地址标签（115,116）的标签存储设备（114），每个地址标签与一个数据存储线（113），分配在数据存储装置（112）中的控制器（117）。控制器（117）设置第一数量的地址标签（115,116），并且配置第一数量的数据存储线（113）以用作具有第一数据存储线尺寸的第一数据存储线，并且设置第二数量的地址标签（115,116），并且配置第二数量的数据存储线（113）以用作具有第二数据存储线尺寸的第二数据存储线。第二数据存储线尺寸与第一数据存储线尺寸不同。

102. 发明公开

EP2721584A1 REAL TIME ON-CHIP TEXTURE DECOMPRESSION USING SHADER PROCESSORS 有权转让
标题翻译：使用阴影处理器实时片上纹理解压缩
公开(公告)号：EP2721584A1
公开(公告)日：2014-04-23
申请号：EP12732897.9
申请日：2012-06-14
申请人： Advanced Micro Devices, Inc.
发明人： IOURCHA, Konstantine , BROTHERS, John, W.
IPC分类号： G06T9/00 , G06T15/00
CPC分类号： G06T9/00 , G06F12/0875 , G06F12/109 , G06F2212/401 , G06F2212/455 , G06F2212/657 , G06T1/20 , G06T15/005
摘要： A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.
摘要翻译：处理单元，方法和介质，用于解压缩或生成图形处理单元（GPU）内的纹理。纹理用诸如JPEG的可变速率压缩方案压缩。压缩纹理从系统内存中检索并传输到GPU上的本地高速缓存存储器，而无需先解压缩。高速缓存利用表来定位压缩纹理内的各个块。解压缩着色器处理器接收压缩块，然后对块进行即时解压缩。然后解压后的块像往常一样由GPU的纹理消耗着色器处理器进行处理。

103. 发明申请

WO2018057109A1 CACHE AND COMPRESSION INTEROPERABILITY IN A GRAPHICS PROCESSOR PIPELINE 审中-公开
标题翻译：图形处理器管道中的缓存和压缩互操作性
公开(公告)号：WO2018057109A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/043950
申请日：2017-07-26
申请人： INTEL CORPORATION
发明人： AKENINE-MOLLER, Tomas, G. , SURTI, Prasoonkumar , KOKER, Altug , PUFFER, David , NILSSON, Jim
IPC分类号： G06T1/60 , G06T1/20 , G06T9/00
CPC分类号： G06F12/0875 , G06F3/0655 , G06F12/0207 , G06F12/084 , G06F12/0842 , G06F17/22 , G06F2212/1024 , G06F2212/302 , G06F2212/401 , G06F2212/455 , G06T1/20 , G06T1/60 , G06T15/005
摘要： Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.
摘要翻译：这里描述了几个实施例，其结合自适应和动态压缩来提供增强数据缓存，以在GPU的输入和输出期间增加存储效率并降低数据的传输带宽。本文描述的技术可以减少访问片外存储器的需要，导致GPU操作的改进的性能和降低的功率。一个实施例提供了一种包括着色引擎的图形处理装置; 一个或多个高速缓存存储器高速缓存控制逻辑，用于控制一个或多个高速缓存存储器中的至少一个; 以及与所述一个或多个高速缓冲存储器耦合的编解码器单元，所述编解码器单元可配置为在存储到所述一个或多个高速缓冲存储器或从所述一个或多个高速缓冲存储器逐出时执行只读表面数据的无损压缩。

104. 发明申请

WO2016167876A1 SUPPORTING MULTI-LEVEL NESTING OF COMMAND BUFFERS IN GRAPHICS COMMAND STREAMS AT COMPUTING DEVICES 审中-公开
标题翻译：在计算机设备的图形命令流中支持多层次的命令缓存
公开(公告)号：WO2016167876A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/018490
申请日：2016-02-18
申请人： INTEL CORPORATION
发明人： NALLURI, Hema Chand , VEMBU, Balaji , BOLES, Jeffery S.
IPC分类号： G06T1/20 , G06F9/30 , G06T1/60
CPC分类号： G06T1/20 , G06F12/00 , G06F12/0811 , G06F12/0875 , G06F2212/1016 , G06F2212/455 , G06T1/60
摘要： A mechanism is described for facilitating multi-level nesting of batch buffers at computing devices. A method of embodiments, as described herein, includes facilitating a hardware extension to accommodate a plurality of batch buffers to engage in a multi-level nesting, where the plurality of batch buffers are associated with a graphics processor of a computing device. The method may further include facilitating the multi-level nesting of the plurality of batch buffers, where the multi-level nesting is spread over a plurality of levels associated with the plurality of batch buffers, where the plurality of levels include more than two levels of nesting associated with more than two batch buffers of the plurality of batch buffers.
摘要翻译：描述了一种机制，用于促进计算设备上批量缓冲区的多级嵌套。如本文所述的实施例的方法包括促进硬件扩展以容纳多个批次缓冲器以参与多级嵌套，其中多个批处理缓冲器与计算设备的图形处理器相关联。该方法还可以包括促进多级批量缓冲器的多级嵌套，其中多级嵌套分布在与多个批量缓冲器相关联的多个级别上，其中多个级别包括多于两级的与多个批次缓冲器中的两个以上批处理缓冲器相关联的嵌套。

105. 发明申请

WO2016089086A1 ELECTRONIC DEVICE AND METHOD FOR CONTROLLING SHAREABLE CACHE MEMORY THEREOF 审中-公开
标题翻译：用于控制其可访问的高速缓存存储器的电子设备和方法
公开(公告)号：WO2016089086A1
公开(公告)日：2016-06-09
申请号：PCT/KR2015/012998
申请日：2015-12-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HWANG, Chanyoung , YANG, Seungjin
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/084 , G06F1/32 , G06F1/3275 , G06F12/0842 , G06F12/0895 , G06F2212/1028 , G06F2212/20 , G06F2212/455 , G06F2212/604 , G06F2212/62 , Y02D10/13
摘要： An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.
摘要翻译：提供了一种用于控制电子设备的共享高速缓冲存储器的电子设备和方法。电子设备包括中央处理单元，该中央处理单元包括至少一个核心处理器，至少一个模块和包括控制器的可共享高速缓存存储器，其中如果中央处理器将控制器作为中央处理单元的高速缓存存储器，单元处于工作模式，并且其中如果中央处理单元的至少一个核心处理器转换到休眠模式，则控制器使得可共享高速缓冲存储器作为至少一个模块的缓冲器。

106. 发明申请

WO2014028109A2 MEMORY SHARING VIA A UNIFIED MEMORY ARCHITECTURE 审中-公开
标题翻译：内存共享通过统一的内存架构
公开(公告)号：WO2014028109A2
公开(公告)日：2014-02-20
申请号：PCT/US2013045657
申请日：2013-06-13
申请人： INTEL CORP , RAO JAYANTH N , SUNDARESAN MURALI
发明人： RAO JAYANTH N , SUNDARESAN MURALI
CPC分类号： G06T11/60 , G06F12/00 , G06F12/0811 , G06F12/1009 , G06F12/1036 , G06F12/1081 , G06F12/109 , G06F2212/455 , G06F2212/6042 , G06F2212/62 , G06F2212/656 , G06T1/20 , G06T1/60 , Y02B60/1225 , Y02D10/13
摘要： A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.
摘要翻译：本文公开了用于在计算设备的中央处理单元（CPU）和图形处理单元（GPU）之间共享存储器的方法和系统。该方法包括在物理存储器内分配表面并将该表面映射到CPU页面表内的多个虚拟存储器地址。该方法还包括将表面映射到I / O设备页表内的多个图形虚拟存储器地址。

107. 发明申请

WO2012174231A1 REAL TIME ON-CHIP TEXTURE DECOMPRESSION USING SHADER PROCESSORS 审中-公开
标题翻译：使用SHADER处理器的实时片上纹理分解
公开(公告)号：WO2012174231A1
公开(公告)日：2012-12-20
申请号：PCT/US2012/042442
申请日：2012-06-14
申请人： ADVANCED MICRO DEVICES, INC. , IOURCHA, Konstantine , BROTHERS, John, W.
发明人： IOURCHA, Konstantine , BROTHERS, John, W.
IPC分类号： G06T9/00 , G06T15/00
CPC分类号： G06T9/00 , G06F12/0875 , G06F12/109 , G06F2212/401 , G06F2212/455 , G06F2212/657 , G06T1/20 , G06T15/005
摘要： A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.
摘要翻译：一种用于在图形处理单元（GPU）内解压缩或生成纹理的处理单元，方法和介质。纹理采用可变速率压缩方案（如JPEG）进行压缩。压缩的纹理从系统内存中检索并传输到GPU上的本地缓存内存，而无需首先解压缩。缓存利用表来定位压缩纹理内的各个块。解压缩着色器处理器接收压缩块，然后对块进行即时解压缩。解压缩的块然后像通常那样由GPU的纹理消耗着色器处理器进行处理。

108. 发明申请

WO2012109770A1 TECHNIQUES TO REQUEST STORED DATA FROM A MEMORY 审中-公开
标题翻译：从存储器中请求存储数据的技术
公开(公告)号：WO2012109770A1
公开(公告)日：2012-08-23
申请号：PCT/CN2011/000254
申请日：2011-02-18
申请人： INTEL CORPORATION (a corporation of Delaware) , WANG, Kebing , YE, Jun , LI, Jianyu
发明人： WANG, Kebing , YE, Jun , LI, Jianyu
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F8/4442 , G06F12/0886 , G06F2212/302 , G06F2212/455 , G06F2212/601 , G06T1/60 , G06T15/04 , G09G5/39
摘要： Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.
摘要翻译：描述技术来基于绘制调用的属性和纹理的访问方向来配置高速缓存行结构。可以考虑绘制调用使用的纹理属性（例如，纹理格式和过滤器类型），采样器和着色器，以确定高速缓存的行大小。访问方向可以考虑减少用于存储样本请求所需的纹素的行数。

109. 发明申请

WO2009145919A1 SHADER COMPLEX WITH DISTRIBUTED LEVEL ONE CACHE SYSTEM AND CENTRALIZED LEVEL TWO CACHE 审中-公开
标题翻译：具有分布式一级缓存系统和集中级两级缓存的SHADER复合
公开(公告)号：WO2009145919A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/003317
申请日：2009-06-01
申请人： ADVANCED MICRO DEVICES, INC. , DELAURIER, Anthony, P. , LEATHER, Mark , HARTOG, Robert, S. , MANTOR, Michael, J. , FOWLER, Mark, C. , ZINI, Marcos, P.
发明人： DELAURIER, Anthony, P. , LEATHER, Mark , HARTOG, Robert, S. , MANTOR, Michael, J. , FOWLER, Mark, C. , ZINI, Marcos, P.
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F2212/302 , G06F2212/455 , G06T1/60 , G09G5/363 , G09G2360/121
摘要： A shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. The level one cache system communicates with the level two cache system via a wide channel memory bus. In addition, the level one cache system can be configured to support dual shader pipe texture filters while maintaining access to the level two cache system. A method utilizing a level one cache system as a primary method of storage with the ability to have the level one cache system read and write a level two cache system when necessary is also presented. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources.
摘要翻译：着色器管道纹理过滤器使用一级缓存系统作为存储的主要方法，但是在必要时能够使一级缓存系统读取和写入二级缓存系统。一级缓存系统通过宽通道存储器总线与二级缓存系统进行通信。此外，一级缓存系统可以配置为支持双重着色器管道纹理过滤器，同时保持对二级缓存系统的访问。还提出了一种利用一级缓存系统作为主要的存储方法，具有使得一级缓存系统在必要时读取和写入二级缓存系统的能力。此外，一级缓存系统可以分配其他资源之间可共享的定义的内存区域。

110. 发明申请

WO2018118364A1 MEMORY CONSISTENCY IN GRAPHICS MEMORY HIERARCHY WITH RELAXED ORDERING 审中-公开
公开(公告)号：WO2018118364A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/063787
申请日：2017-11-29
申请人： APPLE INC.
发明人： DELAURIER, Anthony P. , ANDERSON, Owen C. , SWIFT, Michael J. , MUNSHI, Aaftab A. , POTTER, Terence M.
IPC分类号： G06T1/60
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/084 , G06F2212/455 , G06F2212/621 , G06T1/60
摘要： Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

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