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101. 发明授权

US08363367B2 Electrical overstress protection circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US08363367B2
公开(公告)日：2013-01-29
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

102. 发明申请

US20120261804A1 VERTICAL SUBSTRATE DIODE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE 审中-公开
标题翻译：垂直基板二极管，制造方法和设计结构
公开(公告)号：US20120261804A1
公开(公告)日：2012-10-18
申请号：US13087915
申请日：2011-04-15
申请人： Junjun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Junjun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： H01L29/06 , H01L21/22 , B82Y99/00
CPC分类号： H01L29/861 , H01L21/76256 , H01L27/0255
摘要： A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.
摘要翻译：提供了一种二极管结构，其形成在绝缘体上的绝缘体（SOI）的埋置介质层下，其制造方法及其设计结构。在一个实施例中，二极管结构的p-n结可以有利地以垂直取向布置。阴极包括在P型衬底上形成的N +外延层。阳极包括P基底的有源区。通过埋入介电层形成与阴极和阳极的接触。通过填充有导电插塞的深沟槽实现与阳极的接触。深沟槽还为阴极（以及p-n结）提供电隔离。有利地，本发明的实施例可以在形成其它结构的过程中形成，这些结构还包括沟槽（例如，深沟槽电容器），以便减少在SOI衬底的埋置介质层下形成二极管结构所需的工艺步骤。

103. 发明申请

US20120250195A1 ELECTROSTATIC DISCHARGE POWER CLAMP WITH A JFET BASED RC TRIGGER CIRCUIT 有权
标题翻译：静电放电电源钳位与基于JFET的RC触发电路
公开(公告)号：US20120250195A1
公开(公告)日：2012-10-04
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

104. 发明授权

US08010927B2 Structure for a stacked power clamp having a BigFET gate pull-up circuit 有权
标题翻译：具有BigFET栅极上拉电路的堆叠式功率钳的结构
公开(公告)号：US08010927B2
公开(公告)日：2011-08-30
申请号：US12127245
申请日：2008-05-27
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , H01L23/53 , H01L23/62 , H01L29/66
CPC分类号： G06F17/5045 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译：用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

105. 发明授权

US07772651B2 Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits 失效
标题翻译：绝缘体上半导体高压器件结构，制造这种器件结构的方法，以及高压电路的设计结构
公开(公告)号：US07772651B2
公开(公告)日：2010-08-10
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译：高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将每个栅电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

106. 发明授权

US07646573B2 Method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：改善ESD钳位装置触发和振荡抑制的方法
公开(公告)号：US07646573B2
公开(公告)日：2010-01-12
申请号：US12133424
申请日：2008-06-05
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

107. 发明授权

US08987073B2 Self-protected metal-oxide-semiconductor field-effect transistor 有权
标题翻译：自保护金属氧化物半导体场效应晶体管
公开(公告)号：US08987073B2
公开(公告)日：2015-03-24
申请号：US13546509
申请日：2012-07-11
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/66
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译：金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。栅极结构形成在衬底的顶表面上。第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。第二沟槽横向形成在第一沟槽和第一侧壁之间。第一和第二外延层分别形成在第一和第二沟槽中。形成到作为漏极的第一外延层的接触。第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。

108. 发明授权

US08954306B2 Component behavior modeling using separate behavior model 有权
标题翻译：使用单独行为模型的组件行为建模
公开(公告)号：US08954306B2
公开(公告)日：2015-02-10
申请号：US12826958
申请日：2010-06-30
申请人： Junjun Li , Rahul Nayak
发明人： Junjun Li , Rahul Nayak
IPC分类号： G06G7/48 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5045 , G06F17/5068
摘要： A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.
摘要翻译：提供了行为模型，其被配置为模拟除了组件的组件模型之外的组件的行为的一个方面。行为模型可以包含在用于模拟电路运行的电路模型中。电路模型可以包括组件的组件模型和与组件模型并联或串联的对应行为模型。组件模型和行为模型可以共同模拟电路中组件的所有行为。在一个实施例中，行为模型模拟组件所呈现的回弹行为。

109. 发明授权

US08796731B2 Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure 有权
标题翻译：低泄漏，低电容静电放电（ESD）硅控制背光（SCR），制造方法和设计结构
公开(公告)号：US08796731B2
公开(公告)日：2014-08-05
申请号：US12859801
申请日：2010-08-20
申请人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/861
CPC分类号： H01L29/7412 , H01L27/0262
摘要： A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.
摘要翻译：提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。该方法包括在绝缘体层上提供硅膜。该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

110. 发明授权

US08730624B2 Electrostatic discharge power clamp with a JFET based RC trigger circuit 有权
标题翻译：具有基于JFET的RC触发电路的静电放电电源钳位
公开(公告)号：US08730624B2
公开(公告)日：2014-05-20
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

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